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- Carlsson, Ella, et al.
(författare)
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An evaluation of models for Martian gully formation using remote sensing and in situ measurments of Svalbard analogs.
- 2008
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Ingår i: Lunar and Planetary Science Conference 39. ; XXXIX:1852
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- The newly discovered gully systems on Mars have been found on rather young geologi-cal surfaces such as dunes and polygons. This in combination with the general absence of superimposed impact craters suggests that the gullies are relatively young geological features. Their morphology indicates that they have been eroded by a liquid fluid, most probably water. A recent discovery suggests that gully formation is an ongoing process, which appears to occur even today. This is a paradox since water in current Martian atmospheric conditions cannot be found in a stable form on the surface due to the low pressure and temperature during normal conditions. Several formation mechanisms have been proposed for the Martian gullies such as liquid carbon dioxide reservoirs, shallow liquid water aquifer, melting ground ice, dry landslide, snow melt and deep liquid water aquifer. However, none of these models can alone explain all the gullies discovered on Mars. So far Martian gullies have only been studied from high orbit via satellites. Gullies found in Arctic climates on Earth could be an equitable analog for the Martian gullies and a com-parative analysis could help disclose the formation mechanisms of the Martian gullies as well as their eroding agent.
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| 3. |
- Fredholm, Hanna, et al.
(författare)
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Breast cancer in young women : poor survival despite intensive treatment
- 2009
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Ingår i: PLoS one. - : Public Library of Science (PLoS). - 1932-6203. ; 4:11, s. e7695-
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Tidskriftsartikel (refereegranskat)abstract
- BACKGROUND: Breast cancer is uncommon in young women and correlates with a less favourable prognosis; still it is the most frequent cancer in women under 40, accounting for 30-40% of all incident female cancer. The aim of this study was to study prognosis in young women, quantifying how much stage at diagnosis and management on the one hand, and tumour biology on the other; each contribute to the worse prognosis seen in this age group. METHODOLOGY/PRINCIPAL FINDINGS: In a registry based cohort of women aged 20-69 (n = 22 017) with a primary diagnosis of invasive breast cancer (1992-2005), women aged 20-34 (n = 471), 35-39 (n = 858) and 40-49 (n = 4789) were compared with women aged 50-69 years (n = 15 899). The cumulative 5-year relative survival ratio and the relative excess mortality (RER) were calculated. The cumulative 5-year relative survival ratio was lowest in women aged 20-34. The RER was 2.84 for women aged 20-34 and decreased with increasing age (RER 1.76 and 1.17 for women aged 35-39 and 40-49, respectively). The excess risk was, however, present only in disease stages I and II. For women aged 20-34 with stage I disease RER was 4.63, and 6.70 in the subgroup with tumour size 1-10 mm. The absolute difference in stage I between the youngest and the reference groups amounted to nearly 8%, with a 90% 5-year survival in women aged 20-34. In stages IIa and IIb, the relative excess risk was not as dramatic, but the absolute differences approached 15%. The youngest women with small tumours generally received more aggressive treatment than women in older age groups. CONCLUSIONS: After correction for stage, tumour characteristics and treatment, age remained an independent risk factor for breast cancer death in women <35 years of age. The excess risk for young women was only seen in early stages of disease and was most pronounced in women with small tumours. Young women affected by breast cancer have a high risk of dying compared to their middle-aged counterparts even if diagnosed early and receiving an intense treatment.
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| 4. |
- Fredriksson, Henrik, 1975-, et al.
(författare)
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2.6 Gb/s Over a Four-Drop Bus Using an Adaptive 12-Tap DFE
- 2008
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Ingår i: ESSCIRC 2008 - Proceedings of the 34th European Solid-State Circuits Conference. - Bristol, UK : IOP Institute of Physics. - 9781424423620 - 9781424423613 ; , s. 470-473
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Konferensbidrag (refereegranskat)abstract
- For PC DRAM buses, the number of slots per channel has decreased as data rates have increased. This limits the maximum memory capacity per channel. Signal equalization can be used to increase bit-rates for channels with a large number of slots and offer a cost effective method to solve the memory capacity problem. This paper presents a blind adaptive decision feedback equalizer (DFE) that enables high data-rates with a large number of slots per channel. Measurements at 2.6 Gb/s over a four-drop bus are presented.
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| 8. |
- Fredriksson, Henrik, 1975-, et al.
(författare)
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Blind Adaptive Mixed-Signal DFE for Gb/s, Multi-Drop, Buses
- 2006
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Ingår i: International Symposium on VLSI Design, Automation and Test, 2006. - Piscataway, USA : IEEE Conference Publications Management Group. - 1424401801 - 1424401798 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- This paper presents a mixed signal decision feedback equalizer (DFE) efficiently implementing sign-sign least-mean-square (SS-LMS) coefficient updating, offset estimation and compensation. The equalizer is designed for multi-drop buses and has 16 six bit fully programmable filter coefficients. The equalizer filter is implemented with a novel carry-save-DAC architecture eliminating the carry propagation limiting factor. Measurement results from a test chip are presented showing no transmission errors and good clock skew robustness when receiving data at 700 Mb/s over a heavily polluted channel. The test chip also includes bit error rate (BER) measurement circuits and equalized eye-chart extraction
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| 9. |
- Fredriksson, Henrik, 1975-
(författare)
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Equalization techniques for multi-Gb/s multi-drop buses
- 2007
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The development of electronics is continuously expanding the possibilities of computational power and system complexity. The progress has in the past and in the foreseeable future primarily been achieved by the development of integrated circuit technologies. Though the trend is to integrate more and more functionality on a single chip (usually referred to as the system-on-chip concept). technology. manufacturing. system integration. and enterprise business model considerations prevent the system-on-chip concept to prevail in all electronic systems. Therefore. the continuous progresses in integrated circuit data handling capabilities impose faster inter chip communication.Though the improvements in materials and devices have to some extent fulfilled these increased communication speed requirements, the pace has been slower than the development of the integrated circuits. For many applications, this has made the communication channels between integrated circuits a limiting factor.To tackle these problems, electronic systems tend to utilize more point to point high-speed high quality links for chip-to-chip communication. This approach only partially solves the problem and it can for various reasons not be used for a ll systems. One type of system where high-speed narrow links have been used. but where the dominating bus structure s till is a wide multi-drop structure. is the memory interface of a standard computer. Improvements in the electrical properties of this type of bus have so far been enough to keep up with the increased demands for higher data rates, but it will not be able to do so in the future. This thesis presents work exploiting the possibilities of using equalizing techniques to drastically improve the data handling speed of multi-drop memory buses. The approach has been to accept the speed limiting mechanisms of the multi-drop bus and to exploit the fast deve lopment of integrated circuit's on-chip computational power to enable higher data rates.The thesis analyses the speed limiting factors on a chip-to-chip multi-drop channel. Different equalization techniques (including blind adaptive techniques) are presented and compared from a multi-drop bus point of view. A new equalizer implementation structure is presented and results from test chip measureme nts are included. Different computational abilities for the memory chip and the memory host chip make us suggest the use of asymmetric equalization relying on the reciprocal properties of the channel. Finally. issues related to evaluation of high -speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.
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| 10. |
- Fredriksson, Henrik, 1975-
(författare)
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Improvement Potential and Equalization Circuit Solutions for Multi-drop DRAM Memory Buses
- 2008
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Digital computers have changed human society in a profound way over the last 50 years. Key properties that contribute to the success of the computer are flexible programmability and fast access to large amounts of data and instructions. Effective access to algorithms and data is a fundamental property that limits the capabilities of computer systems. For PC computers, the main memory consists of dynamic random access memory (DRAM). Communication between memory and processor has traditionally been performed over a multi-drop bus.Signal frequencies on these buses have gradually increased in order to keep up with the progress in integrated circuit data processing capabilities. Increased signal frequencies have exposed the inherent signal degradation effects of a multidrop bus structure. As of today, the main approach to tackle these effects has been to reduce the number of endpoints of the bus structure. Though improvements in DRAM memory technology have increased the available memory size at each endpoint, the increase has not been able to fully fulfill the demand for larger system memory capacity. Different bus structural changes have been used to overcome this problem. All are different compromises between access latency, data transmission capacity, memory capacity, and implementation costs.In this thesis we focus on using the signal processing capabilities of a modern integrated circuit technology as an alternative to bus structural changes. This has the potential to give low latency, high memory capacity, and relatively high data transmission capacity at an additional cost limited to integrated circuit blocks. We first use information theory to estimate the unexplored potential of existing multi-drop bus structures. Hereby showing that reduction of the number of endpoints for multi-drop buses, is by no means based on the fundamental limit of the data transmission capacity of the bus structure. Two test-chips have been designed and fabricated to experimentally demonstrate the feasibility of several Gb/s data-rates over multidrop buses, with limited cost overhead and no latency penalty. The test-chips implement decision feedback equalization, adopted for high speed multi-drop use. The equalizers feature digital filter implementations which, in combination with high speed DACs, enable the use of long digital filters for high speed decision feedback equalization. Blind adaptation has also been implemented to demonstrate extraction of channel characteristics during data transmission. The use of single sided equalization has been proposed in order to limit the need for equalization implementation to the host side of a DRAM memory bus. Furthermore, we propose to utilize the reciprocal properties of the communication channel to ensure that single sided equalization can be performed without any channel characterization hardware on the memory chips. Finally, issues related to evaluation of high-speed channels are addressed and the on-chip structures used for channel evaluation in this project are presented.
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