| 1. |
- Goel, Bhavishya, 1981, et al.
(författare)
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Infrastructures for Measuring Power
- 2011
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- Energy-aware resource management requires some means of measuring power consumption. We present three approaches to measuring processor power. The easiest, least intrusive places a power meter between the system and power outlet. Unfortunately, this provides a single system measurement, and acuity is limited by device sampling frequency. Another method samples power at PSU voltage outputs using current transducers. This logs consumption separately per component, but requires custom hardware and an expensive analog acquisition device. A more accurate alternative samples power directly at the processor voltage regulator’s current-sensing pin, but requires motherboard intrusion. We explain implementation of each approach step-by-step.
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| 2. |
- Goel, Bhavishya, 1981
(författare)
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Measurement, Modeling, and Characterization for Power-Aware Computing
- 2014
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Society’s increasing dependence on information technology has resulted in the deployment of vast compute resources. The energy costs of operating these resources coupled with environmental concerns have made power-aware computingone of the primary challenges for the IT sector. Making energy-efficient computing a rule rather than an exception requires that researchers and system designers use the right set of techniques and tools. These involve measuring,modeling, and characterizing the energy consumption of computers at varying degrees of granularity.In this thesis, we present techniques to measure power consumption of computer systems at various levels. We compare them for accuracy and sensitivityand discuss their effectiveness. We test Intel’s hardware power model for estimation accuracy and show that it is fairly accurate for estimating energy consumption when sampled at the temporal granularity of more than tens ofmilliseconds.We present a methodology to estimate per-core processor power consumption using performance counter and temperature-based power modeling and validate it across multiple platforms. We show our model exhibits negligible computationoverhead, and the median estimation errors ranges from 0.3% to 10.1% for applications from SPEC2006, SPEC-OMP and NAS benchmarks. We test the usefulness of the model in a meta-scheduler to enforce power constraint on a system.Finally, we perform a detailed performance and energy characterization of Intel’s Restricted Transactional Memory (RTM). We use TinySTM software transactional memory (STM) system to benchmark RTM’s performance against competing STM alternatives. We use microbenchmarks and STAMP benchmarksuite to compare RTM versus STM performance and energy behavior. We quantify the RTM hardware limitations that affect its success rate. We show that RTM performs better than TinySTM when working-set fits inside the cache and that RTM is better at handling high contention workloads.
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| 3. |
- Goel, Bhavishya, 1981, et al.
(författare)
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Performance and energy analysis of the restricted transactional memory implementation on haswell
- 2014
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Ingår i: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS. - 2332-1237. - 9780769552071 ; , s. 615-624
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Konferensbidrag (refereegranskat)abstract
- Hardware transactional memory implementations are becoming increasingly available. For instance, the Intel Core i7 4770 implements Restricted Transactional Memory (RTM) support for Intel Transactional Synchronization Extensions (TSX). In this paper, we present a detailed evaluation of RTM performance and energy expenditure. We compare RTM behavior to that of the TinySTM software transactional memory system, first by running micro benchmarks, and then by running the STAMP benchmark suite. We find that which system performs better depends heavily on the workload characteristics. We then conduct a case study of two STAMP applications to assess the impact of programming style on RTM performance and to investigate what kinds of software optimizations can help overcome RTM's hardware limitations.
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| 4. |
- Goel, Bhavishya, 1981, et al.
(författare)
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Portable, scalable, per-core power estimation for intelligent resource management
- 2010
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Ingår i: International Green Computing Conference, 2010, Chicago, USA. - 9781424476121 ; , s. 135-146
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Konferensbidrag (refereegranskat)abstract
- Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall).
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| 5. |
- Goel, Bhavishya, 1981, et al.
(författare)
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Techniques to Measure, Model, and Manage Power
- 2012
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Ingår i: Advances in Computers. - 0065-2458. - 9780123965288 ; 87, s. 7-54
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Society's increasing dependence on information technology has resulted in the deployment of vast compute resources. The energy costs of operating these resources coupled with environmental concerns have made energy-aware computing one of the primary challenges for the IT sector. Making energy-efficient computing a rule rather than an exception requires that researchers and system designers use the right set of techniques and tools. These involve measuring, analyzing, and controlling the energy expenditure of computers at varying degrees of granularity. In this chapter, we present techniques to measure power consumption of computer systems at various levels and to compare their effectiveness. We discuss methodologies to estimate processor power consumption using performance-counter-based power modeling and show how the power models can be used for power-aware scheduling. Armed with such techniques and methodologies, we as a research and development community can better address challenges in power-aware management.
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| 6. |
- Keramidas, G., et al.
(författare)
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Embedded reconfigurable computing: The ERA approach
- 2013
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Ingår i: IEEE International Conference on Industrial Informatics (INDIN). - 1935-4576. ; , s. 827-832
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Konferensbidrag (refereegranskat)abstract
- The growing complexity and diversity of embedded systems-combined with continuing demands for higher performance and lower power consumption-places increasing pressure on embedded platforms designers. The target of the ERA project is to offer a holistic, multi-dimensional methodology to address these problems in a unified framework exploiting the inter-and intra-synergism between the reconfigurable hardware (core, memory, and network resources), the reconfigurable software (compiler and tools), and the run-time system. Starting from the hardware level, we design our platform via a structured approach that allows integration of reconfigurable computing elements, network fabrics, and memory hierarchy components. These hardware elements can adapt their composition, organization, and even instruction-set architectures to exploit tradeoffs in performance and power. Appropriate hardware resources can be selected both statically at design time and dynamically at run time. Hardware details are exposed to our custom operating system, our custom runtime system, and our adaptive compiler, and are even visible all the way up to the application level. The design philosophy followed in the ERA project proved efficient enough not only to enable a better choice of power/performance trade-offs but also to support fast platform prototyping of high-efficiency embedded system designs. In this paper, we present a brief overview of the design approach, the major outcomes, and the lessons learned in the ERA project.
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| 7. |
- Själander, Magnus, 1977, et al.
(författare)
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Power-Aware Resource Scheduling in Base Stations
- 2011
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Ingår i: Proceedings of the 19th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems Singapore; 25 July 2011 through 27 July 2011. - 9780769544304 ; , s. 462-465
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Konferensbidrag (refereegranskat)abstract
- Baseband stations for Long Term Evolution (LTE) communication processing tend to rely on over-provisioned resources to ensure that peak demands can be met. These systems must meet user Quality of Service expectations, but during non-peak workloads, for instance, many of the cores could be placed in low-power modes. One key property of such application-specific systems is that they execute frequent, short-lived tasks. Sophisticated resource management and task scheduling approaches suffer intolerable overhead costs in terms of time and expense, and thus lighter-weight and more efficient strategies are essential to both saving power and meeting performance expectations. To this end, we develop a flexible, non-propietary LTE workload model to drive our resource management studies. Here we describe our experimental infrastructure and present early results that underscore the promise of our approach along with its implications on future hardware/software codesign.
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