| 1. |
- Huan, Yuxiang, et al.
(författare)
-
A 101.4 GOPS/W Reconfigurable and Scalable Control-Centric Embedded Processor for Domain-Specific Applications
- 2016
-
Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : IEEE. - 1549-8328 .- 1558-0806. ; 63:12, s. 2245-2256
-
Tidskriftsartikel (refereegranskat)abstract
- Adapting the processor to the target application is essential in the Internet-of-Things (IoT), and thus requires customizability in order to improve energy efficiency and scalability to provide sufficient performance. In this paper, a reconfigurable and scalable control-centric architecture is proposed, and a processor consisting of two cores and an on-chip multi-mode router is implemented. Reconfigurability is enabled by a programmable sequence mapping table (SMT) which reorganizes functional units in each cycle, thus increasing hardware utilization and reducing excessive data movement for high energy efficiency. The router facilitates both wormhole and circuit switching to construct intra- or inter-chip interconnections, providing scalable performance. Fabricated in a 65-nm process, the chip exhibits 101.4 GOPS/W energy efficiency with a die size of 3.5 mm(2). The processor carries out general-purpose processing with a code size 29% smaller than the ARM Cortex M4, and improves the performance of application-specific processing by over ten times when implementing AES and RSA using SMTs instead of general-purpose C. By utilizing the on-chip router, the processor can be interconnected up to 256 nodes, with a single link bandwidth of 1.4 Gbps.
|
|
| 2. |
- Huan, Yuxiang, et al.
(författare)
-
A 61 μa/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things
- 2016
-
Ingår i: International System on Chip Conference. - : IEEE Computer Society. - 9781467390941 ; , s. 235-239
-
Konferensbidrag (refereegranskat)abstract
- This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.
|
|
| 3. |
- Ma, Ning, et al.
(författare)
-
A 101.4 GOPS/W Reconfigurable and Scalable Control-centric Embedded Processor for Domain-specific Applications
- 2016
-
Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781479953400 ; , s. 1746-1749
-
Konferensbidrag (refereegranskat)abstract
- Increasing the energy efficiency and performance while providing the customizability and scalability is vital for embedded processors adapting to domain-specific applications such as Internet of Things. In this paper, we proposed a reconfigurable and scalable control-centric architecture, and implemented the design consisting of two cores and an on-chip multi-mode router in 65 nm technology. The reconfigurability is enabled by the restructurable sequence mapping table (SMT) thus the reorganizable functional units. Owing to the integration of the multi-mode router, on-chip or inter-chip network for multi-/many-core computing can be composed for performance extension on demand even in the post-fabrication stage. Control-centric design simplifies the control logic, shrinks the non-functional units and orchestrates the operations to increase the hard are utilization and reduce the excessive data movement for high energy efficiency. As a result, the processor can both conduct general-purpose processing with 29% smaller code size and application-specific processing with over 10 times performance improvement when implementing AES by SMT. The dual-core processor consumes 19.7 μW/MHz with die size of 3.5 mm2. The achieved energy efficiency is 101.4GOPS/W.
|
|
| 4. |
- Zhang, Wei, et al.
(författare)
-
Hierarchical Design of a Low Power Standing Wave Oscillator Based Clock Distribution Network
- 2016
-
Ingår i: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). - : IEEE conference proceedings. - 9781509010950
-
Konferensbidrag (refereegranskat)abstract
- This paper introduces a hierarchical clock interconnection network with two-level bufferless standing wave resonant clock distribution to minimize the clock power consumption in a synchronous system. The first level is a serpentine network which consists of many coupled standing wave oscillators to distribute clock signals in the whole chip area. The second level is a group of fishbone architectures connected to the standing wave oscillators to route clock signals in the local areas. A clock synthesis flow for the fishbone architecture is also introduced to enable design automation. This fishbone architecture is studied through a pipelined floating-point fused multiply-add module under 28nm standard CMOS process. Simulation results show that, this architecture can reduce more than 30% clock power consumption compared with a traditional buffered clock network.
|
|
