| 1. |
- Buiu, O., et al.
(författare)
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Extracting the relative dielectric constant for "high-k layers" from CV measurements : Errors and error propagation
- 2007
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Ingår i: Microelectronics and reliability. - : Elsevier BV. - 0026-2714 .- 1872-941X. ; 47:4-5, s. 678-681
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Tidskriftsartikel (refereegranskat)abstract
- The paper pursues an investigation of the errors associated with the extraction of the dielectric constant (i.e., kappa value) from capacitance-voltage measurements on metal oxide semiconductor capacitors. The existence of a transition layer between the high-rc dielectric and the silicon substrate is a factor that affects - in general - the assessment of the electrical data, as well as the extraction of rc. A methodology which accounts for this transition layer and the errors related to other parameters involved in the k value extraction is presented; moreover, we apply this methodology to experimental CV results on HfO2/SiOx/Si structures produced in different conditions.
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| 2. |
- Engstrom, O., et al.
(författare)
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Navigation aids in the search for future high-k dielectrics : Physical and electrical trends
- 2007
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 622-626
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Tidskriftsartikel (refereegranskat)abstract
- From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.
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| 3. |
- Engström, Olof, 1943, et al.
(författare)
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A generalised methodology for oxide leakage current metric
- 2008
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Ingår i: Proceeding of 9th European Workshop on Ultimate Integration of Silicon (ULIS), Udine, Italy. - 9781424417308 ; , s. 167-
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Konferensbidrag (refereegranskat)abstract
- From calculations of semiconductor interfacecharge, oxide voltage and tunneling currents for MOSsystems with equivalent oxide thickness (EOT) in therange of 1 nm, rules are suggested for making itpossible to compare leakage quality of different oxideswith an accuracy of a factor 2 – 3 if the EOT is known.The standard procedure suggested gives considerablybetter accuracy than the commonly used method todetermine leakage at VFB+1V for n-type and VFB-1V forp-type substrates.
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| 4. |
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| 5. |
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| 6. |
- Gottlob, H. D. B., et al.
(författare)
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Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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| 7. |
- Gottlob, H. D. B., et al.
(författare)
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Gentle FUSI NiSi metal gate process for high-k dielectric screening
- 2008
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 85:10, s. 2019-2021
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).
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| 8. |
- Hurley, P. K., et al.
(författare)
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Interface defects in HfO2, LaSiOx, and Gd2O3 high-k/metal-gate structures on silicon
- 2008
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Ingår i: Journal of the Electrochemical Society. - : The Electrochemical Society. - 0013-4651 .- 1945-7111. ; 155:2, s. G13-G20
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.
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| 9. |
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| 10. |
- Hurley, P.K., et al.
(författare)
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Interface Defects in HfO2, LaSiOx, and Gd2O3 High-k/MetalGate Structures on Silicon
- 2008
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Ingår i: J. Electrochem. Soc.. ; 155:2, s. G13-G20
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Tidskriftsartikel (refereegranskat)abstract
- In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.
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