| 1. |
- Johansson, Ted, et al.
(författare)
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Influence of SOI-generated stress on BiCMOS performance
- 2006
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 935-942
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Tidskriftsartikel (refereegranskat)abstract
- Two BiCMOS processes were adapted for SOI and the performance of the bipolar devices was studied. Differences in electrical parameters were observed, in particular the current gain, which processing or doping profiles could not explain, but correlated with observed stress in transistors. Simulation of the process flow with stress included revealed that stress was generated to a higher degree in the SOI wafers in the presence of deep trench isolation (DTI). Theoretical estimations and electrical simulations with and without stress yielded results consistent with observed data. Thus, we conclude that the observed differences are caused by process-induced in-plane biaxial stress.
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| 2. |
- Di Benedetto, Luigi, et al.
(författare)
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Strain balance approach for optimized signal-to-noise ratio in SiGe quantum well bolometers
- 2009
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Ingår i: ESSDERC 2009 - Proceedings of the 39th European Solid-State Device Research Conference. - 9781424443536 ; , s. 101-104
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Konferensbidrag (refereegranskat)abstract
- This work presents thermal and electrical characterization of SiGe/Si multi-quantum wells (MQWs) with different layer profiles in complete bolometer structures. The thermal property of the bolometers was studied by measuring thermal coefficient of resistivity (TCR) through I-V curves for five temperatures (25, 40, 55, 80 and 100°C) and for four different pixel areas. The results show a strong dependency of TCR on the Si/SiGe layer thickness and the presence of dopant impurity in the MQW. The noise measurements of MQWs were performed carefully by eliminating all external contributions and the noise spectroscopy provided the noise characteristic parameters. The results demonstrate that the noise depends on the geometric size of the MQW and it increases with decreasing of the pixel area. The investigations show the noise level in the bolometer structures is sensitive to any dopant segregation from the contact layers.
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| 3. |
- Driussi, F., et al.
(författare)
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On the electron mobility enhancement in biaxially strained Si MOSFETs
- 2008
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:4, s. 498-505
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Tidskriftsartikel (refereegranskat)abstract
- This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.
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| 4. |
- Ghandi, Reza, et al.
(författare)
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High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension
- 2009
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Ingår i: IEEE Electron Device Letters. - : Institute of Electrical and Electronics Engineers (IEEE). - 0741-3106 .- 1558-0563. ; 30:11, s. 1170-1172
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Tidskriftsartikel (refereegranskat)abstract
- Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.
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| 5. |
- Haralson, Erik, et al.
(författare)
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NiSi integration in a non-selective base SiGeCHBT process
- 2005
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Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 8:03-jan, s. 245-248
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Tidskriftsartikel (refereegranskat)abstract
- A self-aligned nickel silicide (salicide) process is integrated into a non-selective base SiGeC HBT process. The device features a unique, fully silicided base region that grows laterally under the emitter pedestal. This Ni(SiGe) formed in this base region was found to have a resistivity of 23-24 muOmega cm. A difference in the silicide thickness between the boron-doped SiGeC extrinsic base region and the in situ phosphorous-doped emitter region is observed and further analyzed and confirmed with a blanket wafer silicide study. The silicided device exhibited a current gain of 64 and HF device performance of 39 and 32 GHz for f(t) and f(MAX), respectively.
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| 6. |
- Hållstedt, Julius, et al.
(författare)
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A robust spacer gate process for deca-nanometer high-frequency MOSFETs
- 2006
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:3, s. 434-439
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Tidskriftsartikel (refereegranskat)abstract
- This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.
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| 7. |
- Hållstedt, Julius, et al.
(författare)
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Leakage current reduction in 80 nm biaxially strained Si nMOSFETs on in-situ doped SiGe virtual substrates
- 2007
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Ingår i: ESSDERC 2007 - Proceedings of the 37th European Solid-State Device Research Conference 2008. - 9781424411238 ; , s. 319-322
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Konferensbidrag (refereegranskat)abstract
- We present a comprehensive study of biaxially strained (up to similar to 3 GPa stress) Si nMOSFETs down to 80 nm gatelength. Well behaved 80 nm devices with expected strain-induced electrical enhancement were demonstrated. Special emphasis was put on investigation of substrate junction leakage and source to drain leakage. In-situ doped wells and channel profiles demonstrated superior substrate junction leakage for the relaxed SiGe substrates compared to conventional implantation. The source to drain leakage in 80 nm devices was effectively reduced by increment of channel doping and rotation of the channel direction.
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| 8. |
- Malm, B. Gunnar, et al.
(författare)
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Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base
- 2005
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Ingår i: IEEE Electron Device Letters. - : IEEE Press. - 0741-3106 .- 1558-0563. ; 26:4, s. 246-248
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Tidskriftsartikel (refereegranskat)abstract
- A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R-B was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity. of the Ni(SiGe:C) silicide layer was 24 mu Omega (.) cm. About 50-100 nm of lateral growth of silicide,. underneath the emitter pedestal was observed. DC and HF results with balanced f(T)/f(MAX) values of 41/42 GHz were demonstrated for 0.5 X 10 mu m(2) transistors.
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| 9. |
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| 10. |
- Malm, B. Gunnar, et al.
(författare)
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Noise Properties of High-Mobility, 80 nm Gate Length MOSFETs on Supercritical Virtual Substrates
- 2008
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Ingår i: SIGE, GE, AND RELATED COMPOUNDS 3: MATERIALS, PROCESSING, AND DEVICES. - : The Electrochemical Society. - 9781566776561 ; , s. 529-537
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Konferensbidrag (refereegranskat)abstract
- It was found that for strained Si channel layers of supercritical thickness oil relaxed SiGe virtual substrates, the 1/f noise oil,average is maintained at the same level as in unstrained devices. Short gate length nMOSFETs were analyzed statistically and the noise level variation, across a large number of samples, was similar in strained and unstrained devices. The obtained noise level variation was partly related to gate length fluctuations across the wafer, which was evident from a small V-T fluctuation.
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