| 1. |
- Efavi, J K, et al.
(författare)
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Investigation of NiAlN as gate-material for submicron CMOS technology
- 2004
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359
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Tidskriftsartikel (refereegranskat)abstract
- Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
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| 2. |
- Lemme, Max C., 1970-, et al.
(författare)
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Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs
- 2004
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Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-74:SI, s. 346-350
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Tidskriftsartikel (refereegranskat)abstract
- New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.
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| 3. |
- Lemme, Max C., 1970-, et al.
(författare)
-
Subthreshold characteristics of p-type triple-gate MOSFETs
- 2003
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Ingår i: ESSDERC 2003. - NEW YORK : IEEE. ; , s. 123-126
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Konferensbidrag (refereegranskat)abstract
- The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, output and transfer characteristics of 70nm printed gate length p-MOSFETs with 22nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.
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