| 1. |
- Echtermeyer, T., et al.
(författare)
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Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes
- 2007
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 51:4, s. 617-621
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Tidskriftsartikel (refereegranskat)abstract
- Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.
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| 2. |
- Gottlob, H. D. B., et al.
(författare)
-
0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes
- 2006
-
Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:10, s. 814-816
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.
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| 3. |
- Gottlob, H. D. B., et al.
(författare)
-
Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
- 2006
-
Ingår i: ESSDERC 2006. - 9781424403011 ; , s. 150-153
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Konferensbidrag (refereegranskat)abstract
- Two process concepts for integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd2O3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
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| 4. |
- Gottlob, H. D. B., et al.
(författare)
-
CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics
- 2006
-
Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 50:6, s. 979-985
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Tidskriftsartikel (refereegranskat)abstract
- Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.
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| 5. |
- Gottlob, H D B, et al.
(författare)
-
Introduction of crystalline high-k gate dielectrics in a CMOS process
- 2005
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Ingår i: Journal of Non-Crystalline Solids. - : Elsevier BV. - 0022-3093 .- 1873-4812. ; 351:21-23, s. 1885-1889
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Tidskriftsartikel (refereegranskat)abstract
- In this work we report on methods to introduce crystalline rare-earth (RE) oxides with high (k > 3.9) dielectric constants (high-k) in a CMOS process flow. Key process steps compatible with crystalline praseodymium oxide (Pr2O3) high-k gate dielectric have been developed and evaluated in metal-oxide-semiconductor (MOS) structures and n-MOS transistors fabricated in an adapted conventional bulk process. From capacitance-voltage measurements a dielectric constant of k = 36 has been calculated. Furthermore an alternative process sequence suitable for the introduction of high-k material into silicon on insulator (SOI) MOS-field-effect-transistors (MOSFET) is presented. The feasibility of this process is shown by realization of n- and p-MOSFETs with standard SiO2 gate dielectric as demonstrator. SiO2 gate dielectric can be replaced by crystalline RE-oxides in the next batch fabrication.
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| 6. |
- Gottlob, H. D. B., et al.
(författare)
-
Investigation of high-K gate stacks with epitaxial Gd(2)O(3) and FUSINiSi metal gates down to CET=0.86 nm
- 2006
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Ingår i: Materials Science in Semiconductor Processing. - : Elsevier BV. - 1369-8001 .- 1873-4081. ; 9:6, s. 904-908
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Tidskriftsartikel (refereegranskat)abstract
- Novel gate stacks with epitaxial gadoliniurn oxide (Gd(2)O(3)) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10(-7) A cm(-2) are observed at a capacitance equivalent oxide thickness of CET = 1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd(2)O(3) thickness of 3.1 nm yield current densities down to 0.5 A cm(-2) at V(g) = + 1 V. The extracted dielectric constant for these gate stacks ranges from k = 13 to 14. These results emphasize the potential of NiSi/Gd(2)O(3) gate stacks for future material-based scaling of CMOS technology.
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| 7. |
- Gottlob, H. D. B., et al.
(författare)
-
Leakage current mechanisms in epitaxial Gd(2)O(3) high-k gate dielectrics
- 2008
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Ingår i: Electrochemical and solid-state letters. - : The Electrochemical Society. - 1099-0062 .- 1944-8775. ; 11:3, s. G12-G14
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Tidskriftsartikel (refereegranskat)abstract
- We report on leakage current mechanisms in epitaxial gadolinium oxide (Gd(2)O(3)) high-k gate dielectrics suitable for low standby power logic applications. The investigated p-type metal-oxide-semi con doctor capacitors are gated with complementary-metal-oxide-semiconductor-compatible fully silicided nickel silicide electrodes. The Gd(2)O(3) thickness is 5.9 nm corresponding to a capacitance equivalent oxide thickness of 1.8 nm. Poole-Frenkel conduction is identified as the main leakage mechanism with the high-frequency permittivity describing the dielectric response on the carriers. A trap level of Phi(T) = 1.2 eV is extracted. The resulting band diagram strongly suggests hole conduction to be dominant over electron conduction.
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| 8. |
- Gottlob, H D B, et al.
(författare)
-
Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics
- 2006
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:2, s. 710-714
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Tidskriftsartikel (refereegranskat)abstract
- A "gate first" silicon on insulator (SOI) complementary metal oxide semiconductor process technology for direct evaluation of epitaxial gate dielectrics is described, where the gate stack is fabricated prior to any lithography or etching step. This sequence provides perfect silicon surfaces required for epitaxial growth. The inverted process flow with silicon dioxide (SiO2)/polysilicon gate stacks is demonstrated for gate lengths from 10 mu m down to 40 nm on a fully depleted 25 nm thin SOI film. The interface qualities at the front and back gates are investigated and compared to conventionally processed SOI devices. Furthermore, the subthreshold behavior is studied and the scalability of the gate first approach is proven by fully functional sub-100 nm transistors. Finally, a fully functional gate first metal oxide semiconductor field effect transistor with the epitaxial high-k gate dielectric gadolinium oxide (Gd2O3) and titanium nitride (TiN) gate electrode is presented.
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| 9. |
- Efavi, J K, et al.
(författare)
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Tungsten work function engineering for dual metal gate nano-CMOS
- 2005
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 16:7, s. 433-436
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Tidskriftsartikel (refereegranskat)abstract
- A buffer layer technology for work function engineering of tungsten for dual metal gate Nano-CMOS is investigated. For the first time, tungsten is used as a p-type gate material using 1 nm of sputtered Aluminum Nitride (AlNx) as a buffer layer on silicon dioxide (SiO2) gate dielectric. A tungsten work function of 5.12 eV is realized using this technology in contrast to a mid-gap value of 4.6 eV without a buffer layer. Device characteristics of a p-MOSFET on silicon-on-insulator (SOI) substrate fabricated with this technology are presented.
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| 10. |
- Fuchs, A., et al.
(författare)
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Nanowire fin field effect transistors via UV-based nanoimprint lithography
- 2006
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 24:6, s. 2964-2967
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Tidskriftsartikel (refereegranskat)abstract
- A triple step alignment process for UV nanoimprint lithography (UV-NIL) for the fabrication of nanoscale fin field effect transistors (FinFETs) is presented. An alignment accuracy is demonstrated between two functional layers of less than 20 nm (3 sigma). The electrical characterization of the FinFETs fabricated by a full NIL process demonstrates the potential of UV-NIL for future nanoelectronic devices.
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