| 1. |
- Abdalla, Suliman A
(författare)
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Architecture and circuit design of photon counting readout for X-ray imaging sensors
- 2007
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Hybrid pixel array detectors for X-ray imaging are based on different technologies for sensor and readout electronics. The readout electronics are based on standard CMOS technologies that are experiencing continuously rapid improvements by means of down-scaling the feature sizes, which in turn lead to higher transistor densities, lower power consumption, and faster circuits. For pixel-array imaging sensors the improvements in CMOS technology opens up new possibilities of integrating more functionality in the pixels for local processing of the sensor data. However, new issues related to the tight integration of both analog and digital processing circuits within the small area of a pixel must also be evaluated. The advantages of down-scaling the CMOS technology can be utilized to increase the spatial resolution by reducing the pixel sizes. Recent research indicates however that the bottleneck in reaching further spatial resolution in X-ray imaging sensors may not be limited by the circuit area occupied by the functions necessary in the pixels, but are instead related to problems associated with charge-sharing of charges generated by the sensor which are distributed over a neighbourhood of pixels and will limit the spatial resolution and lead to a distortion of the energy spectrum. In this thesis a mechanism to be implemented in the readout circuits is proposed in order to suppress the charge-sharing effects. The proposed architecture and its circuit implementation are evaluated with respect to circuit complexity (area) and power consumption. For a photon-counting pixel it is demonstrated that the complete pixel, with charge-sharing suppression mechanism, can be implemented using 300 transistors with an idle power consumption of 2.7μW in a 120nm CMOS technology operating with a 1.2V power supply. The improvements in CMOS technology can also be used for increasing the range of applications for X-ray imaging sensors. In this thesis, an architecture is proposed for multiple energy discrimination, called color X-ray imaging. The proposed solution is the result of balancing the circuit complexity and the image quality. The method is based on color sub-sampling with intensity biasing. For three-level energy discrimination, that corresponds to color imaging systems for visible light with R, G, and B color components, the increase in circuit complexity will be only 20% higher than that for the Bayer method but results in significantly better image quality. As the circuit complexity in the digital processing within each pixel is increased, the digitally induced noise may play an increasingly important role for the signal-to-noise ratio in the measurements. In this thesis an initial study is conducted regarding how the digital switching noise affects the analog amplifiers in the photon-counting pixel.
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| 2. |
- Abdalla, Suliman, et al.
(författare)
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Architecture and Circuit Design for Color X-Ray Pixal Array Detector Read-Out Electronics
- 2007
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Ingår i: 24th Norchip Conference, 2006. - New York : IEEE conference proceedings. - 9781424407729 ; , s. 271-276
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Konferensbidrag (refereegranskat)abstract
- This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.
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| 3. |
- Abdalla, Suliman, et al.
(författare)
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Circuit Implementation of Mechanism for Charge-Sharing Suppression for Photon-Counting Pixel Arrays
- 2005
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Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 137-140
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Konferensbidrag (refereegranskat)abstract
- This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel with window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μW when idle. It is implemented in a 120nm CMOS process and the presented results are based on simulations.
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| 4. |
- Alfredsson, Jon, 1977-, et al.
(författare)
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Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
- 2005
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Ingår i: Proceedings of IFIP VLSI-SOC 2005. - : Edith Cowan Univ. ; , s. 229-232
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.
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| 5. |
- Alfredsson, Jon, et al.
(författare)
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Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold
- 2006
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - : IEEE conference proceedings. - 9780780393899 ; , s. 4341-4344
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins
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| 6. |
- Alfredsson, Jon, et al.
(författare)
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Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs
- 2006
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Ingår i: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3. - 9781424403943 ; , s. 1296-1299
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.
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| 7. |
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| 8. |
- Alfredsson, Jon
(författare)
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Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
- 2007
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Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract
- All who is involved in electronic design knows that one of the critical issues in today’s electronic is the power consumption. Designers are always looking for new approaches in order to reduce currents while still retain performance. Floating-gate (FGMOS) circuits have previously been shown to be a promising technique to improve speed and still keep the power consumption low when power supply is reduced below subthreshold voltage for the transistors. In this thesis, the goal is to determine how good floating-gate circuits can be compared to conventional static CMOS when the circuits are working in subthreshold. The most interesting performance parameters are speed and power consumption and specifically the Energy-Delay Product (EDP) that is a combination of those two. To get a view over how the performance varies and how good the FGMOS circuits are at their best case, the circuits have been designed and simulated for best case performance. The investigation also includes trade-offs with speed and power consumption for better performance, how to select floating-gate capacitances, how a large circuit fan-in will affect performance and also the influence of different kinds of refresh circuits. The first simulations of the FGMOS circuits in a 0.13 μm process have several interesting results. First of all, in the best case it is shown that FGMOS has potential to achieve up to 260 times in better EDP-performance compared to CMOS at 150 mV power supply. Continuing with simulations of FGMOS capacitances shows that minimum floating-gate capacitance can be as small as 400 fF and more realistic performance shows that EDP is 37 times better for FGMOS (with parasitic capacitances included). Other aspects of FGMOS design have been to look at how refresh circuits will affect performance (semi-floating-gate circuits) and how a larger fan-in will change noise margin and EDP. It turns out that refresh circuits with the same transistor size does not give a noticeable change in performance while an increase of 8 times in size will give between 5 and 10 times wors EDP. When it comes to fan-in the simulations shows that a maximum fan-in of 5 is possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to 150 mV. Finally, it should be kept in mind that tuning the performance of FGMOS circuits with trade-offs and by changing the floating-gate voltages to achieve results like the ones stated above will also always affect the noise margins, NM, of the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a fabricated circuit with that NM may not be as functional as simulations suggests. The probability to design functional FGMOS circuits in subthreshold does not seem to be a problem though.
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| 9. |
- Alfredsson, Jon, et al.
(författare)
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Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
- 2007
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Ingår i: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA. - : IEEE conference proceedings. - 9780769527628 ; , s. 314-317
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Konferensbidrag (refereegranskat)abstract
- For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)
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| 10. |
- Aunet, Snorre, et al.
(författare)
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Real-time reconfigurable subthreshold CMOS perceptron
- 2008
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Ingår i: IEEE Transactions on Neural Networks. - 1045-9227 .- 1941-0093. ; 19:4, s. 645-657
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T = 1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on bow the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.
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