| 1. |
- Andreani, Pietro, et al.
(författare)
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A 1.8 GHz CMOS VCO with reduced phase noise
- 2001
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Ingår i: 2001 Symposium on VLSI Circuits, 2001. Digest of Technical Papers.. - 4891140143 ; , s. 121-122
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Konferensbidrag (refereegranskat)abstract
- A 2 V, 6 mA, 15% tuning range, 1.8 GHz VCO implemented in a standard 0.35 μm CMOS process is presented. The phase noise of the VCO has been greatly reduced by means of on-chip filters and one off-chip low frequency inductor. The phase noise measured at 3 MHz offset from the carrier is between -141.5 dBc/Hz and -138.5 dBc/Hz over the whole tuning range
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| 2. |
- Andreani, Pietro, et al.
(författare)
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A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
- 2001
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Ingår i: Proceedings of the IEEE 2001 Custom Integrated Circuits Conference. - 0018-9200. ; , s. 197-200
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Konferensbidrag (refereegranskat)abstract
- A 1.4 V, 9 mA monolithic LC-tank voltage-controlled oscillator (VCO) fabricated in a standard 0.35 μm CMOS process is presented. The VCO is tunable between 2.0 GHz and 2.37 GHz, and displays a phase noise between -140 dBc/Hz and -138 dBc/Hz at a 3 MHz offset frequency across the whole tuning range. This low phase noise is achieved through the use of an on-chip LC filter and an off-chip low frequency inductor, which totally remove the noise of the tail current source. The phase noise improvement due to the off-chip inductor is between 2 dB and 6 dB, increasing with higher oscillation frequencies
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| 3. |
- Andreani, Pietro, et al.
(författare)
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Noise optimization of an inductively degenerated CMOS low noise amplifier
- 2001
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Ingår i: IEEE Transactions on Circuits and Systems - 2, Analog and Digital Signal Processing. - : Institute of Electrical and Electronics Engineers (IEEE). - 1057-7130. ; 48:9, s. 835-841
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a technique for substantially reducing the noise of a CMOS low noise amplifier implemented in the inductive source degeneration topology. The effects of the gate induced current noise on the noise performance are taken into account, and the total output noise is strongly reduced by inserting a capacitance of appropriate value in parallel with the amplifying MOS transistor of the LNA. As a result, very low noise figures become possible already at very low power consumption levels
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| 4. |
- Andreani, Pietro, et al.
(författare)
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Tail current noise suppression in RF CMOS VCOs
- 2002
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200. ; 37:3, s. 342-348
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents the experimental results of two different techniques, inductive degeneration and capacitive filtering, for reducing the phase noise in tail-biased RF CMOS voltage-controlled oscillators (VCOs). Both techniques prevent the low-frequency tail current noise from being converted into phase noise. The techniques are applied to two distinct VCO designs, showing that the largest phase noise reduction (up to 6-7 dB at 3-MHz offset frequency from the carrier) is achieved via inductive degeneration. Capacitive filtering, however, also substantially reduces the phase noise at high offset frequencies and may therefore become a valid alternative to inductive degeneration, as discrete capacitors are of more common use than discrete inductors.
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| 5. |
- Cijvat, Ellie, et al.
(författare)
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CMOS Transceiver Front-Ends in Mobile Communication Handsets : Architectures and Building Blocks
- 2004
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- For mobile communication systems in the low-GHz range, CMOS has increasingly become the technology of choice, and the level of integration in mobile handsets has risen. The use of off-chip components, which increases the handset assembly time and costs, is preferably avoided. However, integrating a complete transceiver on a single chip leads to disturbances between building blocks. This imposes new and more stringent requirements on building block and transceiver performance, as well as impacts the choice of transceiver architecture.In the general introduction, an overview is given of front-end receiver and transmitter aspects as well as RF CMOS technology. This includes the impact of mobile communication system specifications on architectures and building blocks, transistor and monolithic inductor modeling, and disturbance issues. Special attention is given to power amplifiers, the most challenging building blocks in CMOS transceivers. Papers I, II and III address CMOS receiver front-end aspects and implementations, while in papers IV and V design and challenges of CMOS power amplifiers are described.
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| 6. |
- Cijvat, Pieternella, et al.
(författare)
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A fully integrated 2.45 GHz 0.25 mu m CMOS power amplifier
- 2003
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Ingår i: Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003.. - : IEEE Press. - 0780381637 ; , s. 1094-1097
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Konferensbidrag (refereegranskat)abstract
- A fully integrated differential class-AB power amplifier has been designed in a 0.25 um CMOS technology. It is intended for medium output power ranges such as Bluetooth class 1, and has an operating frequency of 2.45 GHz. By using two parallel output stages that can be switched on or off, a high efficiency can be achieved for both high and low output power levels. The simulated maximum output power is 22.7 dBm, while the maximum power-added efficiency is 22%.
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| 7. |
- Hegazi, Emad, et al.
(författare)
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A filtering technique to lower LC oscillator phase noise
- 2001
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200. ; 36:12, s. 1921-1930
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Tidskriftsartikel (refereegranskat)abstract
- Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.
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| 8. |
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| 9. |
- Karimi-Sanjaani, Ali, et al.
(författare)
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A 2GHz merged CMOS LNA and mixer for WCDMA
- 2001
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Ingår i: Symposium on VLSI Circuits, 2001. Digest of Technical Papers.. - 4891140143 ; , s. 19-22
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Konferensbidrag (refereegranskat)
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| 10. |
- Phansathitwong, Kittichai, et al.
(författare)
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Performance trade-offs in designing a dual-band CMOS IEEE 802.11A/B frontend
- 2004
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Ingår i: Proceedings. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems (IEEE Cat. No.04EX916). - 0780386604 ; , s. 333-336
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Konferensbidrag (refereegranskat)abstract
- This paper describes trade-offs involved in designing a dual-band CMOS frontend for wireless local-area network (WLAN). Three 0.18μm CMOS frontends have been investigated, a single-band frontend at the 2.4 GHz ISM band, a single-band frontend at the 5 GHz U-NII band and a dual-band frontend. The study shows that employing a dual-band frontend yields satisfactory results, although some compromises regarding the performance in the lower frequency band have to be made
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