| 1. |
- Andersson, Martin, et al.
(författare)
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IC-Project and Verification Course: Teaching Top Down Analog/Mixed Signal Design
- 2007
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Ingår i: Proceedings of the Swedish System-on-Chip Conference.
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This paper describes a project course that focuses on the design of analog and mixed signal circuits through a systematic top down design flow. In the project, the student will be involved in the planning, modeling, circuit level design, physical level implementation and measurement verification of for example a successive approximation (SA) ADC or a class-D audio amplifier. Throughout the project, the project members will improve their design skills and create an understanding for the importance of a systematic top-down design methodology at the different levels of the design flow.
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| 2. |
- Andersson, Martin, et al.
(författare)
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Teaching Top Down Design of Analog/Mixed Signal ICs Through Design Projects
- 2007
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Ingår i: FIE 2007: 37th annual Frontiers in education conference - global engineering: knowledge without borders, opportunities without passports, Proceedings. - 0190-5848. ; , s. 40-43
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Konferensbidrag (refereegranskat)abstract
- This paper describes a project course that focuses on the design of analog and mixed signal circuits through a systematic top down design flow. In the project, the student will be involved in the planning, modeling, circuit level design, physical level implementation and measurement verification of for example a successive approximation (SA) ADC or a class-D audio amplifier. Throughout the project, the project members will improve their design skills and create an understanding for the importance of a systematic top-down design methodology at the different levels of the design flow.
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| 3. |
- Aniktar, H, et al.
(författare)
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850/900/1800/1900MHz Quad-Band CMOS Medium Power Amplifier
- 2006
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Ingår i: Proceedings of European Microwave Week 2006. ; , s. 403-406
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Konferensbidrag (refereegranskat)abstract
- This paper presents a two-stage quad-band CMOS RF power amplifier. The power amplifier is fabricated in a 0.25 mum CMOS process. The measured 1-dB compression point between 800 and 900 MHz is 15 dBm plusmn 0.2 dB with maximum 18% PAE, and between 1800 and 1900MHz is 17.5dBm plusmn 0.7dB with maximum 17% PAE. The measured gains in the two bands are 23.6 dB plusmn 0.7 dB and 13 dB plusmn 2.1 dB, respectively.
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| 4. |
- Aniktar, H, et al.
(författare)
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A Class-AB 1.65GHz-2GHz Broadband CMOS Medium Power Amplifier
- 2005
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Ingår i: Proceedings of Norchip 2005.
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Konferensbidrag (refereegranskat)abstract
- In this paper a single stage broadband CMOS RF power amplifier is presented. The power amplifier is fabricated in a 0:25¹m CMOS process. Measurements with a 2:5V supply voltage show an output power of 18:5 dBm with an associated PAE of 16% at the 1-dB compression point. The measured gain is 5.1 § 0:5 dB from 1.65 to 2 GHz. Simulated and measured results agree reasonably well.
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| 5. |
- Aniktar, Huseyin, et al.
(författare)
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A CMOS power amplifier using ground separation technique
- 2007
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Ingår i: Proceedings of 7th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. - 0780397657 ; , s. 281-284
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Konferensbidrag (refereegranskat)abstract
- This work presents an on-chip ground separation technique for power amplifiers. The ground separation technique is based on separating the grounds of the amplifier stages on the chip and thus any parasitic feedback paths are removed. Simulation and experimental results show that the technique makes the amplifier less sensitive to bondwire inductance, and consequently improves the stability and performance. A two-stage CMOS RF power amplifier for WCDMA mobile phones is designed using the proposed on-chip ground separation technique. The power amplifier is fabricated in a 0.25mum CMOS process. It has a measured 1-dB compression point between 1920MHz and 1980MHz of 21.3plusmn0.5dBm with a maximum PAE of 24%. The amplifier has sufficiently low ACLR for WCDMA (-33 dB) at an output power of 20 dBm
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| 6. |
- Aspemyr, Lars, et al.
(författare)
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25 GHz and 28 GHz wide tuning range130 nm CMOS VCOs with ferroelectric varactors
- 2007
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Ingår i: [Host publication title missing]. - 9781424413072 ; , s. 30-33
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Konferensbidrag (refereegranskat)abstract
- Two 130nm CMOS VCOs with ferroelectric varactors are presented. The cross-coupled VCO-cores are flip-chip mounted on silicon carriers with integrated inductors and tunable ferroelectric varactors. The output frequency of the first VCO is tunable from 23.4 GHz to 26.1 GHz, corresponding to a tuning range of 11 %. The phase noise of this VCO, tuned to its center frequency, measures -117 dBC/Hz at 1 MHz offset and the power consumption is 18 mW. The second VCO is tunable from 25.8 GHz to 30.5 GHz, corresponding to a tuning range of 17 %. The phase noise at center frequency for this design measures -109 dBc/Hz and the power consumption is 5.3 mW.
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| 7. |
- Aspemyr, Lars, et al.
(författare)
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A 15 GHz and a 20 GHz low noise amplifier in 90 nm RF CMOS
- 2006
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Ingår i: Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems. - 0780394720 ; , s. 387-390
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Konferensbidrag (refereegranskat)abstract
- The design and measured performance of two low-noise amplifiers at 15 GHz and 20 GHz realized in a 90 nm RF-CMOS process are presented in this work. The 15 GHz LNA achieves a power gain of 12.9 dB, a noise figure of 2.0 dB and an input referred third-order intercept point (IIP3) of -2.3 dBm. The 20 GHz LNA has a power gain of 8.6 dB, a noise figure of 3.0 dB and an IIP3 of 5.6 dBm. Compared to previously reported designs, these two LNAs show lower noise figure at lower power consumption.
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| 8. |
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| 9. |
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| 10. |
- Atalla, E, et al.
(författare)
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An all-digital ΣΔ--frequency discriminator of arbitrary order
- 2006
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Ingår i: IEEE International Symposium on Circuits and Systems, ISCAS 2006. Proceedings.. - 0780393899
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Konferensbidrag (refereegranskat)abstract
- In this paper, we propose an all-digital frequency synthesizer architecture, based on an all-digital ΣΔ-frequency discriminator. The new all-digital synthesizer is compared to previously published work. The architecture of the ΣΔ-frequency discriminator is verified using behavioral simulation.
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