| 1. |
- Tobin, Stephen, et al.
(författare)
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Nondestructive Assay Data Integration with the SKB-50 Assemblies - FY16 Update
- 2016
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Rapport (övrigt vetenskapligt/konstnärligt)abstract
- A project to research the application of non-destructive assay (NDA) techniques for spent fuel assemblies is underway at the Central Interim Storage Facility for Spent Nuclear Fuel (for which the Swedish acronym is Clab) in Oskarshamn, Sweden. The research goals of this project contain both safeguards and non-safeguards interests. These nondestructive assay (NDA) technologies are designed to strengthen the technical toolkit of safeguard inspectors and others to determine the following technical goals more accurately; Verify initial enrichment, burnup, and cooling time of facility declaration for spent fuel assemblies; Detect replaced or missing pins from a given spent fuel assembly to confirm its integrity; and Estimate plutonium mass and related plutonium and uranium fissile mass parameters in spent fuel assemblies. Estimate heat content, and measure reactivity (multiplication).
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| 2. |
- Abdulaziz, Mohammed, 1983, et al.
(författare)
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A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS
- 2019
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480 .- 1557-9670. ; 67:4, s. 1588-1600
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Tidskriftsartikel (refereegranskat)abstract
- © 2019 IEEE. This paper presents a millimeter-wave (mm-wave) phase-locked loop (PLL), with an output frequency centered at 54.65 GHz. It demonstrates a mode-switching architecture that considerably improves the lock time, by seamlessly switching between a low-noise mode and a fast-locking mode that is only used during settling. The improvement is used to counteract the increased lock-time caused by cycle-slips that results from using a high reference frequency of 2280 MHz, which is several hundred times the loop bandwidth. Such a reference frequency alleviates the noise requirements on the PLL and is readily available in 5G systems, from the radio frequency PLL. The mm-wave PLL is implemented in a low-power 28-nm fully depleted silicon-on-insulator CMOS process, and its active area is just 0.19 mm 2 . The PLL also features a novel double injection-locked divide-by-3 circuit and a charge-pump mismatch compensation scheme, resulting in state-of-the-art power consumption, and jitter performance in the low-noise mode. In this mode, the in-band phase noise is between-93 and-96 dBc/Hz across the tuning range, and the integrated jitter is between 176 and 212 fs. The total power consumption of the mm-wave PLL is only 10.1 mW, resulting in a best-case PLL figure-of-merit (FOM) of-245 dB. The lock time in low-noise mode is up to 12μs, which is improved to 3μs by switching to the fast-locking mode, at the temporary expense of a power consumption increase to 15.1 mW, an integrated jitter increase to between 245 and 433 fs, and an FOM increase to between-235 and-240 dB.
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| 3. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Cellular Receiver Front-End with Blocker Sensing
- 2016
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Ingår i: IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2016. - 9781467386517
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Konferensbidrag (refereegranskat)abstract
- A receiver front-end supporting contiguous and non-contiguous intra-band carrier aggregation scenarios with a fully integrated spectrum sensor that can detect both in-gap and out-of-band blockers has been implemented in 65nm CMOS technology. An NF of 2.5dB is achieved using a noise canceling LNTA, and linearized OTAs are used to achieve an IIP3 improvement of up to 6.5dB in-band and 11dB at the filter band edge. The spectrum sensor can detect blocker levels in 22 steps of 9MHz between -100MHz and 100MHz IF. The system consumes between 36.6mA and 57.6mA from a 1.2V supply.
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| 4. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Linearization Technique for Differential OTAs
- 2017
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 64:9, s. 1002-1006
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm 2 and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/ Hz‾‾‾√ , and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
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| 5. |
- Ahmad, Waqas, et al.
(författare)
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A Fully Integrated 26dBm Linearized RF Power Amplifier in 65nm CMOS Technology
- 2015
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Konferensbidrag (refereegranskat)abstract
- In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7dB, output referred 1-dB compression point by 4dB, and adjacent channel leakage ratio (ACLR) by 4.5 dB. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 dBm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 dB, and the output referred 1-dB compression point is 25.4 dBm. The ACLR1 (5 MHz offset) is better than -33 dBc while transmitting a 23dBm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm 2 of chip area.
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| 6. |
- Ahmad, Waqas, et al.
(författare)
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CMOS Adaptive TIA with Embedded Single-Ended to Differential Conversion for Analog Optical Links
- 2015
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Ingår i: 2015 IEEE International Symposium on Circuits and Systems (ISCAS). - 9781479983919
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Konferensbidrag (refereegranskat)abstract
- A variable gain transimpedance amplifier (TIA) is presented featuring single-ended to differential conversion by means of negative feedback. The proposed topology also ensures stability when amplifier gain is varied. Furthermore, effective input capacitance of the TIA is reduced by using a positive capacitive feedback. The circuit is intended for intermediate frequency (IF) over fiber systems, but can be readily adapted for other applications. When simulated with a photodiode capacitance of 1.4 pF, the TIA exhibits a tunable gain range of 51 to 73dBΩ with a bandwidth of 550 MHz. The circuit designed in a standard 65nm CMOS process consuming 4mA from a 1.2V supply, achieves a spurious free dynamic range (SFDR) of 109dB·Hz 2/3 at 100 MHz.
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| 7. |
- Ahmad, Waqas, et al.
(författare)
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CMOS Integrated Remote Antenna Unit for Fiber-Fed Distributed MIMO Systems
- 2017
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 65:1, s. 173-186
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Tidskriftsartikel (refereegranskat)abstract
- A fully integrated remote antenna unit (RAU) intended for fiber-fed distributed multiple-input multiple-output systems is presented. The circuit is designed for narrowband (60 MHz) time-division duplex systems, where an IF over fiber approach is chosen to facilitate the use of low-cost optical components and integrated photodetectors. A novel antenna switch control scheme is introduced, which enables the use of an integrated antenna switch instead of a bulky off chip circulator. The reference frequency signal is distributed in the fiber together with user data and used by a phase-locked-loop-based frequency synthesizer to generate the local oscillator signal inside the RAU, hence synchronizing all RAUs of the distributed antenna system. At an operating frequency of 2.1 GHz, the measured optical-to-electrical conversion gain of the downlink is 71.7 dB, the error vector magnitude is 3.2%, and the adjacent channel leakage ratio is 39.2 dBc at an output power of +3 dBm for a 16-quadrature amplitude modulation (16-QAM) long-term evolution downlink signal. The uplink has a gain of 32.5 dB, a noise figure of 3.5 dB, and an in-band third-order intercept point of -12 dBm. Implemented in a standard 65-nm CMOS process, the complete RAU occupies just 2 mm2 of die area and consumes 146 mW during downlink signal transmission and 122 mW during uplink signal reception.
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| 8. |
- Bondarik, Alexander, et al.
(författare)
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A Bond Wire Connection Implementation at mm-Wave Active Microstrip Antenna
- 2019
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Ingår i: IEEE Microwave and Wireless Components Letters. - 1531-1309. ; 29:6, s. 427-429
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Tidskriftsartikel (refereegranskat)abstract
- A bond wire to microstrip line transition, featuring two impedance transformers, is presented for a mm-wave microstrip antenna and power amplifier (PA) integration using conventional bond wires. Simulated return loss bandwidth for the transition is 4 GHz with a minimum insertion loss of 1 dB. Measurement results for the designed active antenna are compared with measurements for a passive antenna and a standalone PA. The maximum gain is 29 dBi, compared with 16.7-dBi passive antenna maximum gain. The half-power gain bandwidth is 7%. The measured active antenna radiation pattern is in good agreement with simulations. The maximum deembedded PA output power is close to 9 dBm.
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| 9. |
- Bondarik, Alexander, et al.
(författare)
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Microstrip antenna array integrated with 60 GHz band CMOS injection locked power amplifier
- 2016
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Ingår i: 2016 10th European Conference on Antennas and Propagation, EuCAP 2016. - 9788890701863
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Konferensbidrag (refereegranskat)abstract
- A microstrip antenna integration with a power amplifier is presented for the 60 GHz band. The antenna is a single layer 4×4 square patches array. The power amplifier is injection locked, designed in a 65 nm CMOS technology, with single-ended input and output signals. The integration is realized by means of bond wire connections. The antenna and the power amplifier are fabricated, characterized and measured separately. The integrated design is fabricated and measured, results are de-embedded to extract the power amplifier parameters and to compare with separate device measurements. At 56.5 GHz the integrated sample has about 12 dB gain increase with respect to the antenna sample without power amplifier. The presented design is targeting 60 GHz band wireless communication system applications.
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| 10. |
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