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| 2. |
- Vasen, T., et al.
(författare)
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InAs nanowire GAA n-MOSFETs with 12-15 nm diameter
- 2016
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Ingår i: 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. - 9781509006373 ; 2016-September
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Konferensbidrag (refereegranskat)abstract
- InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-All-Around (GAA) MOSFETs with d = 12-15 nm are demonstrated. Ion = 314 μA/μm, and Ssat =68 mV/dec was achieved at Vdd = 0.5 V (Ioff = 0.1 μA/μm). Highest gm measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between gm, Ron, and Imin are discussed.
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| 3. |
- Barker, D., et al.
(författare)
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Individually addressable double quantum dots formed with nanowire polytypes and identified by epitaxial markers
- 2019
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 114:18
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Tidskriftsartikel (refereegranskat)abstract
- Double quantum dots (DQDs) hold great promise as building blocks for quantum technology as they allow for two electronic states to coherently couple. Defining QDs with materials rather than using electrostatic gating allows for QDs with a hard-wall confinement potential and more robust charge and spin states. An unresolved problem is how to individually address these QDs, which is necessary for controlling quantum states. We here report the fabrication of DQD devices defined by the conduction band edge offset at the interface of the wurtzite and zinc blende crystal phases of InAs in nanowires. By using sacrificial epitaxial GaSb markers selectively forming on one crystal phase, we are able to precisely align gate electrodes allowing us to probe and control each QD independently. We hence observe textbooklike charge stability diagrams, a discrete energy spectrum, and electron numbers consistent with theoretical estimates and investigate the tunability of the devices, finding that changing the electron number can be used to tune the tunnel barrier as expected by simple band diagram arguments.
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| 4. |
- Passlack, M., et al.
(författare)
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Core-shell tfet developments and tfet limitations
- 2019
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Ingår i: 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019. - 9781728109428
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Konferensbidrag (refereegranskat)abstract
- Tunneling field-effect transistors (TFET) based on a vertical gate-All-Around (VGAA) nanowire (NW) architecture with a core-shell (CS) structure have been explored for future CMOS applications. Performance predictions based on a tight-binding mode-space NEGF technique include a drive current \mathrm{I}-{\mathrm{o}\mathrm{n}} of 6.7\ \mu \mathrm{A} (NW diameter \mathrm{d}= 10.2\ \mathrm{nm}) at \mathrm{V}-{\mathrm{dd}}=0.3\ \mathrm{V} under low power (LP) conditions (\mathrm{I}-{\mathrm{off}}=1 \mathrm{pA}) for an InAs/GaSb CS TFET. This compares to Si nMOSFET \mathrm{I}-{\mathrm{on}} =2.3\ \mu \mathrm{A} at \mathrm{V}-{\mathrm{dd}}=0.55\ \mathrm{V}(\mathrm{d}=6\ \mathrm{nm}). On the experimental side, scaling of vertical CS NWs resulted in smallest dimensions of \mathrm{d}-{\mathrm{c}}= 17 nm (GaSb core) and \mathrm{t}-{\mathrm{sh}}=3 nm (InAs shell) for a total diameter of 23 nm. VGAA CS nFETs demonstrated drive current of up to 40\ \mu \mathrm{A} (\mathrm{V}-{\mathrm{d}}=0.3\ \mathrm{V}) and subthreshold swing \mathrm{SS}=40\mathrm{mV}/\mathrm{dec}(\mathrm{V}-{\mathrm{d}}=10\mathrm{mV}) for NW diameters between 35-50 nm. Although key TFET properties such as current drive and subthermal SS have been demonstrated using a VGAA CS architecture for the first time, experimental results still lag predictions. An intrinsic relationship between band-To band-Tunneling (BTBT) and \mathrm{D}-{\mathrm{it}} related trap assisted tunneling (TAT) was found which imposes challenging \mathrm{D}-{\mathrm{it}} requirements, in particular for LP \mathrm{I}-{\mathrm{off}} specifications. Complexity of fabrication and a material system foreign to CMOS manufacturing further impact prospects of TFET technology.
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| 5. |
- Potts, H., et al.
(författare)
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Electrical control of spins and giant g-factors in ring-like coupled quantum dots
- 2019
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Ingår i: Nature Communications. - : Springer Science and Business Media LLC. - 2041-1723. ; 10:1
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Tidskriftsartikel (refereegranskat)abstract
- Emerging theoretical concepts for quantum technologies have driven a continuous search for structures where a quantum state, such as spin, can be manipulated efficiently. Central to many concepts is the ability to control a system by electric and magnetic fields, relying on strong spin-orbit interaction and a large g-factor. Here, we present a mechanism for spin and orbital manipulation using small electric and magnetic fields. By hybridizing specific quantum dot states at two points inside InAs nanowires, nearly perfect quantum rings form. Large and highly anisotropic effective g-factors are observed, explained by a strong orbital contribution. Importantly, we find that the orbital contributions can be efficiently quenched by simply detuning the individual quantum dot levels with an electric field. In this way, we demonstrate not only control of the effective g-factor from 80 to almost 0 for the same charge state, but also electrostatic change of the ground state spin.
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| 6. |
- Vasen, T., et al.
(författare)
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Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
- 2019
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Ingår i: Scientific Reports. - : Springer Science and Business Media LLC. - 2045-2322. ; 9:1
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Tidskriftsartikel (refereegranskat)abstract
- Tunneling Field-Effect Transistors (TFET) are one of the most promising candidates for future low-power CMOS applications including mobile and Internet of Things (IoT) products. A vertical gate-all-around (VGAA) architecture with a core shell (C-S) structure is the leading contender to meet CMOS footprint requirements while simultaneously delivering high current drive for high performance specifications and subthreshold swing below the Boltzmann limit for low power operation. In this work, VGAA nanowire GaSb/InAs C-S TFETs are demonstrated experimentally for the first time with key device properties of subthreshold swing S = 40 mV/dec (Vd = 10 mV) and current drive up to 40 μA/wire (Vd = 0.3 V, diameter d = 50 nm) while dimensions including core diameter d, shell thickness and gate length are scaled towards CMOS requirements. The experimental data in conjunction with TCAD modeling reveal interface trap density requirements to reach industry standard off-current specifications.
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| 7. |
- Webb, J. L., et al.
(författare)
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Imaging Atomic Scale Dynamics on III-V Nanowire Surfaces during Electrical Operation
- 2017
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Ingår i: Scientific Reports. - : Springer Science and Business Media LLC. - 2045-2322. ; 7:1
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Tidskriftsartikel (refereegranskat)abstract
- As semiconductor electronics keep shrinking, functionality depends on individual atomic scale surface and interface features that may change as voltages are applied. In this work we demonstrate a novel device platform that allows scanning tunneling microscopy (STM) imaging with atomic scale resolution across a device simultaneously with full electrical operation. The platform presents a significant step forward as it allows STM to be performed everywhere on the device surface and high temperature processing in reactive gases of the complete device. We demonstrate the new method through proof of principle measurements on both InAs and GaAs nanowire devices with variable biases up to 4 V. On InAs nanowires we observe a surprising removal of atomic defects and smoothing of the surface morphology under applied bias, in contrast to the expected increase in defects and electromigration-related failure. As we use only standard fabrication and scanning instrumentation our concept is widely applicable and opens up the possibility of fundamental investigations of device surface reliability as well as new electronic functionality based on restructuring during operation.
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