| 1. |
- Johansson, Håkan, 1969-, et al.
(författare)
-
Filter structures composed of all-pass and FIR filters for interpolation and decimation by a factor of two
- 1999
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Ingår i: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - 1057-7130 .- 1558-125X. ; 46:7, s. 896-905
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Tidskriftsartikel (refereegranskat)abstract
- This paper introduces filter structures for interpolation and decimation by a factor of two. The structures are derived by using the frequency-response masking approach, in which the overall filter makes use of a periodic model filter, its complementary filter, and two masking filters. The periodic model filters are obtained by replacing each delay element in a model filter with M delay elements in cascade. The model filter is a half-band infinite-impulse response (IIR) filter composed of two all-pass filters in parallel, whereas the masking filters are linear-phase finite-impulse response (FIR) filters. In the final interpolator and decimator structures the filtering takes plate at the lowest of the two sampling rates involved. The corresponding overall filter can be designed by separately optimizing a half-band IIR filter and a linear-phase FIR filter. Both nonlinear-phase and approximately linear-phase filters are considered. One advantage of the proposed filter structures over conventional half-band IIR filter structures is that their maximal sample frequency is M times higher, which may be utilized to increase the speed in an implementation and/or to reduce the power consumption via power supply voltage scaling techniques. In the case of approximately linear-phase filters, the computational complexity can be reduced as well. Several design examples are included demonstrating the properties and advantages of the proposed filter structures
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| 2. |
- Johansson, Håkan, et al.
(författare)
-
High-speed lattice wave digital filters for interpolation and decimation
- 1996
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Ingår i: Proc. National Conf. on Radio Science and Communication, RVK'96. ; , s. 543-547
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Bit-serial arithmetic is often advantageous both in terms of small chip area and low power consumption. When using bit-serial arithmetic for implementation of recursive digital filters, the maximal sample frequency is inversely proportional to the coefficient word lengths of the filters. For high-speed applications it is therefore essential to find filter structures with short coefficients. One way to do this is to use cascaded low-order filters instead of one high-order filter. Problems arise though when the cascaded filters are to be used for interpolation and decimation, since the straightforward realization increases the workload due to the different sample rates involved. However, we have developed a novel realization technique which keep the workload at a minimum with the additional possibility to use a high sample frequency. A digital filter for both interpolation and decimation, realized using this novel technique applied on two cascaded lattice wave digital filters, has been implemented. The filter can be used for sample rate conversions between 25 and 50 MHz.
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| 3. |
- Johansson, Håkan, 1969-, et al.
(författare)
-
High-speed recursive digital filters based on frequency masking techniques
- 1999
-
Ingår i: National Conf. Radio Science RVK,1999. ; , s. 357-361
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Konferensbidrag (refereegranskat)abstract
- High-speed recursive digital filters are of interest for applications focusing on high-speed as well as low power consumption because excess speed can be traded for low power consumption through the use of power supply voltage scaling techniques. This paper gives an overview of high-speed recursive digital filters based on frequency masking techniques.
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| 4. |
- Johansson, Håkan, 1969-, et al.
(författare)
-
High-speed recursive filter structures composed of identical all-pass subfilters for interpolation, decimation, and QMF banks with perfect magnitude reconstruction
- 1999
-
Ingår i: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - 1057-7130 .- 1558-125X. ; 46:1, s. 16-28
-
Tidskriftsartikel (refereegranskat)abstract
- High-speed recursive filter structures for interpolation and decimation with factors of two, and quadrature mirror filter (QMF) banks with perfect magnitude reconstruction, are proposed. The structures are composed of identical all-pass subfilters that are interconnected via extra multipliers. For the case of interpolation and decimation filters, the overall transfer function corresponds in the simplest case to several half-band infinite-impulse response (IIR) filters in cascade. To achieve a smaller passband ripple than for a cascade design, a design procedure that has been used earlier for single-rate filters is used. In this approach, the design is split into designs of a prototype finite-impulse response (FIR) filter and a half-band IIR filter. For the case of QMF banks, the design is again separated into designs of a prototype FIR filter and a half-band IIR filter. One major advantage of the proposed filter structures over the corresponding conventional (half-band filter) structures is that the required coefficient word length for the all-pass filters is substantially reduced, implying that the maximal sample frequency can he substantially increased for a given VLSI technology. Further, for interpolation and decimation, the arithmetic complexity may be reduced in comparison with both the conventional structures and straightforward cascade structures. Simple recurrence formulas for computation of the interconnecting multipliers, given the overall transfer function, are derived. Several examples are included which compare the proposed structures with the corresponding conventional and straightforward cascade structures.
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| 5. |
- Johansson, Håkan, 1969-
(författare)
-
Synthesis and Realization of High-Speed Recursive Digital Filters
- 1998
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Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Recursive digital filters restrict the sample frequency at which an implementation of the filters can operate. This bound is determined by the ratio between the number of delay elements and the operation latency in the recursive loops of the filters. The bound can be increased by using recursive filters for which the maximal sample frequency is higher than for conventional filters, so called high-speed filters. Such filters are also candidates for low power consumption since excess speed may be converted into low power consumption through power supply voltage scaling techniques. High-speed recursive digital filters can be obtained by increasing the number of delay elements and/or decreasing the latency in the recursive loops of the filters. In this thesis we introduce new recursive digital filters to this end. These are based on two different approaches. In the first one, the filters are derived by using frequency masking techniques. Here, the filter structures make use of periodic model filters and, possibly periodic, masking filters. Using these techniques, the recursive parts automatically contain a number of delay elements in the loops which increases the maximal sample frequency substantially. Earlier, only some special cases of these techniques have been considered for narrow-band and wideband filtering. We generalize one of these techniques and extend them to arbitrary bandwidths and to interpolation and decimation filters, and Hilbert transformers. For these techniques both IIR and FIR filters are used. We also extend the techniques to the use of only IIR filters, the motivation being that this can reduce the arithmetic complexity. One advantage of frequency masking techniques is that they are not based upon pole-zero cancellations, which is inherent in and a potential drawback of algorithm transformation techniques.In the second approach the structures are composed of identical allpass subfilters that are interconnected via multipliers. The maximal sample frequency is increased since the coefficient sensitivity of the allpass subfilters is reduced, implying a reduced operational latency in the recursive loops. This technique has earlier been used for single-rate filters. We extend it to interpolation and decimation filters, filter banks with perfect magnitude reconstruction, and Hilbert transformers.All filter structures introduced in this thesis make use of allpass filters, possibly in combination with FIR filters. An advantage of this is that robust filters can be obtained by using wave digital filters (WDFs) for the allpass filters. There is also a large freedom to choose structures for both the allpass and FIR filters that are suitable for the problem at hand.
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| 6. |
- Johansson, Håkan, 1969-, et al.
(författare)
-
Wave digital filter structures for high-speed narrow-band and wide-band filtering
- 1999
-
Ingår i: IEEE transactions on circuits and systems. 2, Analog and digital signal processing (Print). - 1057-7130 .- 1558-125X. ; 46:6, s. 726-741
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Tidskriftsartikel (refereegranskat)abstract
- Wave digital filter (WDF) structures for high-speed narrow-band and wide-band filtering are introduced. The narrow-band filter is composed of a periodic model filter and one or several, possibly periodic, masking filters in cascade. Lattice and bireciprocal lattice WDF filters are used for the model and masking filters, respectively. The wide-band filter consists of a narrow-band filter in parallel with an all-pass filter. The overall filters can be designed by separately designing the model and masking filters. The filters obtained in this approach also serve as good initial filters for further optimization. Both nonlinear and approximately linear phase filters are considered. One major advantage of the new filters over the corresponding conventional filters is that they have a substantially higher maximal sample frequency. In the case of approximately linear phase, the computational complexity can also be reduced. Further, the use of bireciprocal lattice wave digital (WD) masking filters also makes it possible to reduce the complexity, compared with the case in which FIR masking filters are used. Several design examples and a discussion of finite wordlength effects are included for demonstrating the properties of the new filters.
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| 7. |
- Karlsson, Magnus, et al.
(författare)
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A robust differential logic style with NMOS logic nets
- 1997
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Ingår i: Proc. IEE Int. Workshop on Signal Processing, IWSSIP'97. ; , s. 61-64
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Konferensbidrag (refereegranskat)abstract
- In this paper a new dynamic differential logic style is presented. A non-precharged single phase clocking scheme is used. The logic is suitable for high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS and merged with the latches. The logic style is also robust for clock slope and yield a data noise margin equal to Vdd/2.
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| 8. |
- Karlsson, Magnus, et al.
(författare)
-
Design and implementation of a complex multiplier using distributed arithmetic
- 1997
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Ingår i: Proc. IEEE Workshop on Signal Processing Systems, SIPS'97. - 0780338065 ; , s. 222-231
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Konferensbidrag (refereegranskat)abstract
- We propose an efficient scheme for implementing a complex multiplier based on distributed arithmetic. A modified bit-serial shift-accumulator for distributed arithmetic is also proposed for computing a*b+c, where a, b and c are complex numbers. The shift-accumulator is highly regular and modular and consists of only three types of bit-slices, each of which consists of only three types of blocks, multiplexers, exclusive OR gates, and latches. The implementation is done using a robust differential single-phase clocked logic style suitable for high-speed and low power operation. The resulting implementation of the complex multiplier has a maximum clock frequency of 250 MHz, consumes 70 mW, and occupies a chip area of 0.5 mm2 in a double-metal 0.8 μm process. The coefficient word length and the data word length are 12 bits and 16 bits, respectively
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| 9. |
- Karlsson, Magnus, et al.
(författare)
-
Implementation of bit-serial adders using robust differential logic
- 1997
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Ingår i: Proc. NORCHIP'97. ; , s. 366-373
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Konferensbidrag (refereegranskat)abstract
- In this paper two bit-serial carry save adders are implemented using a recently proposed differential logic style. The clocking scheme uses a single clock phase with non-precharged stages of logic that may be merged with the latches or the flip-flops. A novel flip-flop structure is used in one of the adders, which significantly lowers the number of clocked transistors. The logic style used in the adder realizations suits high speed and low power operation in both bit-serial and bit-parallel implementations, since all logic nets are purely in NMOS. The logic style is also robust for clock slope and yields a data noise margin equal to Vdd/2. The adders reached a maximal clock frequency of 300 MHz in a 0.8 mm process with a 3.0 V power supply voltage.
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| 10. |
- Karlsson, Magnus, et al.
(författare)
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Low-swing charge recycle bus drivers
- 1998
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Ingår i: Proc. 1998 IEEE Int. Symp. on Circuits and Systems, ISCAS'98. - 0780344553 ; , s. II-117-II-120
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Konferensbidrag (refereegranskat)abstract
- In this paper two robust bus drivers combining low-swing and semi-adiabatic charge recycling technique are presented. The drivers use a novel concept with Schmitt-triggers as voltage sensors. Hence, voltage references are not required. The drivers reduces the power consumption by 55 and 72 percent, respectively.
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