| 1. |
- Hållstedt, Julius, et al.
(författare)
-
Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels
- 2006
-
Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:6, s. 466-468
-
Tidskriftsartikel (refereegranskat)abstract
- The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.
|
|
| 2. |
- Hållstedt, Julius, et al.
(författare)
-
Noise and mobility characteristics of bulk and fully depleted SOI pMOSFETs using Si or SiGe channels
- 2006
-
Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 3:7, s. 67-72
-
Tidskriftsartikel (refereegranskat)abstract
- State of the art bulk and fully depleted SOI Si and SiGe channel pMOSFET devices with gate lengths ranging from 0.1 to 200 μm were fabricated and analyzed in terms of drain current drivability, mobility and noise performance. In general the SOI devices demonstrated superior mobility and significantly reduced I/f noise compared to bulk devices maintaining a well controlled short channel effects due to the ultra thin body.
|
|
| 3. |
- von Haartman, Martin, et al.
(författare)
-
Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate
- 2006
-
Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 53:4, s. 836-846
-
Tidskriftsartikel (refereegranskat)abstract
- Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-kappa dielectric stacks (Al2O3, Al2O3/HfAlOx/Al2O3 and Al2O3/HfO2/Al2O3) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as P0lY-Si/SiO2/Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-kappa material (Al2O3, HfO2, HfAlOx) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/f noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/f noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/f-noise origin.
|
|
| 4. |
- von Haartman, Martin, 1976-
(författare)
-
Low-frequency noise characterization, evaluation and modeling of advanced Si- and SiGe-based CMOS transistors
- 2006
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- A wide variety of novel complementary-metal-oxide-semiconductor (CMOS) devices that are strong contenders for future high-speed and low-noise RF circuits have been evaluated by means of static electrical measurements and low-frequency noise characterizations in this thesis. These novel field-effect transistors (FETs) include (i) compressively strained SiGe channel pMOSFETs, (ii) tensile strained Si nMOSFETs, (iii) MOSFETs with high-k gate dielectrics, (iv) metal gate and (v) silicon-on-insulator (SOI) devices. The low-frequency noise was comprehensively characterized for different types of operating conditions where the gate and bulk terminal voltages were varied. Detailed studies were made of the relationship between the 1/f noise and the device architecture, strain, device geometry, location of the conduction path, surface cleaning, gate oxide charges and traps, water vapour annealing, carrier mobility and other technological factors. The locations of the dominant noise sources as well as their physical mechanisms were investigated. Model parameters and physical properties were extracted and compared. Several important new insights and refinements of the existing 1/f noise theories and models were also suggested and analyzed. The continuing trend of miniaturizing device sizes and building devices with more advanced architectures and complex materials can lead to escalating 1/f noise levels, which degrades the signal-to-noise (SNR) ratio in electronic circuits. For example, the 1/f noise of some critical transistors in a radio receiver may ultimately limit the information capacity of the communication system. Therefore, analyzing electronic devices in order to control and find ways to diminish the 1/f noise is a very important and challenging research subject. We present compelling evidence that the 1/f noise is affected by the distance of the conduction channel from the gate oxide/semiconductor substrate interface, or alternatively the vertical electric field pushing the carriers towards the gate oxide. The location of the conduction channel can be varied by the voltage on the bulk and gate terminals as well by device engineering. Devices with a buried channel architecture such as buried SiGe channel pMOSFETs and accumulation mode MOSFETs on SOI show significantly reduced 1/f noise. The same observation is made when the substrate/source junction is forward biased which decreases the vertical electric field in the channel and increases the inversion layer separation from the gate oxide interface. A 1/f noise model based on mobility fluctuations originating from the scattering of electrons with phonons or surface roughness was proposed. Materials with a high dielectric constant (high-k) is necessary to replace the conventional SiO2 as gate dielectrics in the future in order to maintain a low leakage current at the same time as the capacitance of the gate dielectrics is scaled up. In this work, we have made some of the very first examinations of 1/f noise in MOSFETs with high-k structures composed by layers of HfO2, HfAlOx and Al2O3. The 1/f noise level was found to be elevated (up to 3 orders of magnitude) in the MOSFETs with high-k gate dielectrics compared to the reference devices with SiO2. The reason behind the higher 1/f noise is a high density of traps in the high-k stacks and increased mobility fluctuation noise, the latter possibly due to noise generation in the electron-phonon scattering that originates from remote phonon modes in the high-k. The combination of a TiN metal gate, HfAlOx and a compressively strained surface SiGe channel was found to be superior in terms of both high mobility and low 1/f noise.
|
|
| 5. |
- Östling, Mikael, et al.
(författare)
-
Device integration issues towards 10 nm MOSFETs
- 2006
-
Ingår i: 2006 25TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, VOLS 1 AND 2, PROCEEDINGS. - NEW YORK, NY : IEEE. - 142440116X ; , s. 25-30
-
Konferensbidrag (refereegranskat)abstract
- An overview of critical integration issues for future generation MOSFETs towards 10 nm gate length is presented. Novel materials and innovative structures are discussed. Implementation of high K gate dielectrics is presented and device performance is demonstrated for TiN metal gate surface channel SiGe MOSFETs with a gate stack based on ALD-formed HfO(2)/Al(2)O(3). Low frequency noise properties for those devices are also analyzed. A selective SiGe epitaxy process for low resistivity source/drain contacts has been developed and implemented in pMOSFETs. A spacer pattering technology using optical lithography to fabricate sub 50 nm high-frequency MOSFETs and nanowires is demonstrated, Finally ultra thin body Sol devices with high mobility SiGe channels are demonstrated.
|
|
