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Design of Cost-Effi...
Design of Cost-Efficient SRAM Cell in Quantum Dot Cellular Automata Technology
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- Bhat, Soha Maqbool (author)
- Department of Electrical and Electronics Engineering, Mahindra University, Hyderabad, 500043, India
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- Ahmed, Suhaib (author)
- Department of Electronics and Communication Engineering, Baba Ghulam Shah Badshah University, Rajouri 185234, India
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- Bahar, Ali Newaz (author)
- Department of Information and Communication Technology (ICT), Mawlana Bhashani Science and Technology University, Tangail, 1902, Bangladesh; Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada
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- Wahid, Khan A. (author)
- Department of Electrical and Computer Engineering, University of Saskatchewan, Saskatoon, SK S7N5A9, Canada
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- Otsuki, Akira (author)
- Luleå tekniska universitet,Geovetenskap och miljöteknik,Facultad de Ingeniería y Ciencias, Universidad Adolfo Ibáñez, Diagonal Las Torres 2640, Peñalolén, Santiago, 7941169, Chile; Neutron Beam Technology Team, RIKEN Center for Advanced Photonics, RIKEN, Wako, 351-0198, Japan
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- Singh, Pooran (author)
- Department of Electrical and Electronics Engineering, Mahindra University, Hyderabad, 500043, India
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(creator_code:org_t)
- 2023-01-11
- 2023
- English.
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In: Electronics. - : MDPI. - 2079-9292. ; 12:2
- Related links:
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https://ltu.diva-por... (primary) (Raw object)
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https://urn.kb.se/re...
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https://doi.org/10.3...
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Abstract
Subject headings
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- SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order.
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik -- Annan elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering -- Other Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
- NATURVETENSKAP -- Data- och informationsvetenskap -- Datorteknik (hsv//swe)
- NATURAL SCIENCES -- Computer and Information Sciences -- Computer Engineering (hsv//eng)
Keyword
- cost-efficient
- low power dissipation
- memory cell
- QCA cell
- QCADesigner
- Avfallsteknik
- Waste Science and Technology
Publication and Content Type
- ref (subject category)
- art (subject category)
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