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A chip for lineariz...
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
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- Andreani, Pietro (author)
- Lund University,Lunds universitet,Institutionen för elektro- och informationsteknik,Institutioner vid LTH,Lunds Tekniska Högskola,Department of Electrical and Information Technology,Departments at LTH,Faculty of Engineering, LTH
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Sundström, Lars (author)
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Karlsson, Niklas (author)
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Svensson, Mikael (author)
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(creator_code:org_t)
- 1999
- 1999
- English.
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In: Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, 1999. ISCAS '99.. - 0780354710 ; 1, s. 346-349
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Abstract
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- This paper presents a custom chip for linearization of RF power amplifiers using digital predistortion. The chip has been implemented in a standard digital 0.8 μm CMOS process with standard static cells and single-phase clocking. A systolic complex multiplier based on distributed arithmetic constitutes the core of the chip. The nonlinear function is realized with a look-up table containing complex gain factors applied to the complex multiplier. The maximum clock frequency was found by means of simulation to be 105 MHz corresponding to 21 Msamples/s throughput with 3 W power consumption using 5 V supply voltage. The fabricated chip is fully functional and has been measured up to 60 MHz clock frequency with 825 mW power consumption with 3.3 V supply voltage. Operation at 1.5 V supply voltage allows 10 MHz clock frequency with 35 mW power consumption
Subject headings
- TEKNIK OCH TEKNOLOGIER -- Elektroteknik och elektronik (hsv//swe)
- ENGINEERING AND TECHNOLOGY -- Electrical Engineering, Electronic Engineering, Information Engineering (hsv//eng)
Publication and Content Type
- kon (subject category)
- ref (subject category)
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