| 11. |
- Liu, Lizheng, et al.
(författare)
-
A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
- 2018
-
Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 26:10, s. 2143-2154
-
Tidskriftsartikel (refereegranskat)abstract
- The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.
|
|
| 12. |
- Lu, H., et al.
(författare)
-
An optical dynamic study of MAPbBr3 single crystals passivated with MAPbCl3/I3-MAPbBr3 heterojunctions
- 2017
-
Ingår i: Physical Chemistry, Chemical Physics - PCCP. - : Royal Society of Chemistry. - 1463-9076 .- 1463-9084. ; 19:6, s. 4516-4521
-
Tidskriftsartikel (refereegranskat)abstract
- Recently, perovskite based solar cells have attracted lots of research interest, some of which is in the passivation of perovskite surfaces, particularly the heterojunction based surface passivation. In this study, the optical dynamics of MAPbBr3 single crystals with and without heterojunction passivation were studied systematically by means of a time-resolved spectroscopic technique for the first time. The emission lifetime of MAPbBr3 single crystals under two-photon (1064 nm) excitation is a few orders of magnitude longer than that measured under one-photon (355 nm or 532 nm) excitation. Interestingly, with surface passivation, the lifetime measured at 355 nm excitations could be tuned significantly, whereas the lifetime change under 1064 nm excitations was considerably less. Our results give a direct evidence of surface quench by comparing the lifetimes before and after surface passivation. Furthermore, the results demonstrate that proper MAPbCl3-MAPbBr3 heterojunctions can dramatically reduce the recombination channels in the surface region, which can be potentially useful for perovskite based solar cells, light emitting diodes (LED), and sensitive detectors.
|
|
| 13. |
- Ma, Ning, et al.
(författare)
-
A 101.4 GOPS/W Reconfigurable and Scalable Control-centric Embedded Processor for Domain-specific Applications
- 2016
-
Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781479953400 ; , s. 1746-1749
-
Konferensbidrag (refereegranskat)abstract
- Increasing the energy efficiency and performance while providing the customizability and scalability is vital for embedded processors adapting to domain-specific applications such as Internet of Things. In this paper, we proposed a reconfigurable and scalable control-centric architecture, and implemented the design consisting of two cores and an on-chip multi-mode router in 65 nm technology. The reconfigurability is enabled by the restructurable sequence mapping table (SMT) thus the reorganizable functional units. Owing to the integration of the multi-mode router, on-chip or inter-chip network for multi-/many-core computing can be composed for performance extension on demand even in the post-fabrication stage. Control-centric design simplifies the control logic, shrinks the non-functional units and orchestrates the operations to increase the hard are utilization and reduce the excessive data movement for high energy efficiency. As a result, the processor can both conduct general-purpose processing with 29% smaller code size and application-specific processing with over 10 times performance improvement when implementing AES by SMT. The dual-core processor consumes 19.7 μW/MHz with die size of 3.5 mm2. The achieved energy efficiency is 101.4GOPS/W.
|
|
| 14. |
|
|
| 15. |
- Ma, Ning, et al.
(författare)
-
Design and Implementation of Multi-mode Routers for Large-scale Inter-core Networks
- 2016
-
Ingår i: Integration. - : Elsevier. - 0167-9260 .- 1872-7522. ; 53, s. 1-13
-
Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)abstract
- Constructing on-chip or inter-silicon (inter-die/inter-chip) networks to connect multiple processors extends the system capability and scalability. It is a key issue to implement a flexible router that can fit into various application scenarios. This paper proposes a multi-mode adaptable router that can support both circuit and wormhole switching with supplying flexible working strategies for specific traffic patterns in diverse applications. The limitation of mono-mode switched routers is shown at first, followed by algorithm exploration in the proposed router for choosing the proper working strategy in a specific network. We then present the performance improvement when applying the mixed circuit/wormhole switching mode to different applications, and analyze the image decoding as a case study. The multi-mode router has been implemented with different configurations in a 65 nm CMOS technology. The one with 8-bit flit width is demonstrated together with a multi-core processor to show the feasibility. Working at 350 MHz, the average power consumption of the whole system is 22 mW.
|
|
| 16. |
- Ma, Ning, et al.
(författare)
-
Implementing MVC Decoding on Homogeneous NoCs : Circuit Switching or Wormhole Switching
- 2015
-
Konferensbidrag (refereegranskat)abstract
- To implement multiview video decoding on network on-chip (NoC) based homogeneous multicore architectures, the selection of switching techniques for routers is one of the most important aspects for design space exploration. Circuit switching and wormhole switching are two most feasible switching techniques for on-chip networks. To choose the suitable switching technique, we perform the comparison on decoding speed of the whole system, link utilization and delay between circuit switching and wormhole switching for implementing eight-view QVGA video decoding on 4 × 4 NoCs at 30 fps. The required link bandwidths are both around 800 Mbps with the similar network utilization and delay. We conclude that, to implement multiview video decoding on homogeneous NoCs, circuit switching is more suitable considering the similar performance and lower cost compared with wormhole switching.
|
|
| 17. |
- Ma, Ning
(författare)
-
Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency.To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs.Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW.When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes.In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.
|
|
| 18. |
- Magliulo, M., et al.
(författare)
-
A nanotube/polymer composite biosensing thin-film transistor platform for C-reactive protein detection
- 2015
-
Ingår i: IEEE-NANO 2015 - 15th International Conference on Nanotechnology. - : IEEE conference proceedings. - 9781467381550 ; , s. 1282-1284
-
Konferensbidrag (refereegranskat)abstract
- In the present study, a back-gate thin-film transistor (TFT) based on a single-walled carbon nanotubes (SWCNTs)/poly(9,9-dioctylfluorene-co-bithiophene) (F8T2) composite semiconductor is proposed as electronic label-free immunosensor for the detection of the C-reactive protein (CRP). The nano-composite semiconducting ultra-thin film is deposited on the channel area of the TFT and is functionalized with a monoclonal anti-CRP antibody coating acting as biorecognition layer. The immunesensor was then used for the selective detection of the CRP both in phosphate buffered saline (PBS) solution and in human serum samples. The proposed immunosensor exhibits high current (10 - 20 μA) and good field-effect carriers mobility. Furthermore, the CRP could be revealed at a detection limit as low as 1 mg/L and in a wide dynamic range (from 0.4 nM to 2.2 μM).
|
|
| 19. |
- Mao, Jia
(författare)
-
Radio and Sensor Interfaces for Energy-autonomous Wireless Sensing
- 2016
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Along with rapid development of sensing and communication technology, Internet of Things (IoTs) has enabled a tremendous number of applications in health care, agriculture, and industry. As the fundamental element, the wireless sensing node, such as radio tags need to be operating under micro power level for energy autonomy. The evolution of electronics towards highly energy-efficient systems requires joint efforts in developing innovative architectures and circuit techniques. In this dissertation, we explore ultra-low power circuits and systems for micropower wireless sensing in the context of IoTs, with a special focus on radio interfaces and sensor interfaces. The system architecture of UHF/UWB asymmetric radio is introduced firstly. The active UWB radio is employed for the tag-to-reader communication while the conventional UHF radio is used to power up and inventory the tag. On the tag side, an ultra-low power, high pulse swing, and power scalable UWB transmitter is studied. On the reader side, an asymmetric UHF/UWB reader is designed. Secondly, to eliminate power-hungry frequency synthesis circuitry, an energy-efficient UWB transmitter with wireless clock harvesting is presented. The transmitter is powered by an UHF signal wirelessly and respond UWB pulses by locking-gating-amplifying the sub-harmonic of the UHF signal. 21% locking range can be achieved to prevent PVT variations with -15 dBm injected power. Finally, radio-sensing interface co-design is explored. Taking the advantage of RC readout circuit and UWB pulse generator, the sensing information is directly extracted and transmitted in the time domain, exploiting high time-domain resolution UWB pulses. It eliminates the need of ADC of the sensor interface, meanwhile, reduces the number of bits to be transmitted for energy saving. The measurement results show that the proposed system exhibits 7.7 bits ENOB with an average relative error of 0.42%.
|
|
| 20. |
- Matindoust, S., et al.
(författare)
-
Food quality and safety monitoring using gas sensor array in intelligent packaging
- 2016
-
Ingår i: Sensor Review. - : Emerald Group Publishing Limited. - 0260-2288 .- 1758-6828. ; 36:2, s. 169-183
-
Tidskriftsartikel (refereegranskat)abstract
- Purpose - This paper aims to study different possibilities for implementing easy-to-use and cost-effective micro-systems to detect and trace expelled gases from rotten food. The paper covers various radio-frequency identification (RFID) technologies and gas sensors as the two promoting feasibilities for the tracing of packaged food. Monitoring and maintaining quality and safety of food in transport and storage from producer to consumer are the most important concerns in food industry. Many toxin gases, even in parts per billion ranges, are produced from corrupted and rotten food and can endanger the consumers' health. To overcome the issues, intelligent traceability of food products, specifically the packaged ones, in terms of temperature, humidity, atmospheric conditions, etc., has been paid attention to by many researchers. Design/methodology/approach - Food poisoning is a serious problem that affects thousands of people every year. Poisoning food must be recognized early to prevent a serious health problem. Contaminated food is usually detectable by odor. A small gas sensors and low-cost tailored to the type of food packaging and a communication device for transmitting alarm output to the consumer are key factors in achieving intelligent packaging. Findings - Conducting polymer composite, intrinsically conducting polymer and metal oxide conductivity gas sensors, metal- oxide-semiconductor field-effect transistor (MOSFET) gas sensors offer excellent discrimination and lead the way for a new generation of "smart sensors" which will mould the future commercial markets for gas sensors. Originality/value - Small size, low power consumption, short response time, wide operating temperature, high efficiency and small area are most important features of introduced system for using in package food.
|
|
