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Träfflista för sökning "WFRF:(Lemme Max C. 1970 ) "

Sökning: WFRF:(Lemme Max C. 1970 )

  • Resultat 51-72 av 72
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51.
  • Lemme, Max C., 1970-, et al. (författare)
  • Nanoscale TiN metal gate technology for CMOS integration
  • 2006
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1551-1554
  • Tidskriftsartikel (refereegranskat)abstract
    • A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.
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52.
  • Lemme, Max C., 1970-, et al. (författare)
  • Non-planar devices for nanoscale CMOS
  • 2007
  • Ingår i: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 19-32
  • Konferensbidrag (refereegranskat)abstract
    • In this paper, various concepts of multi-gate transistors are discussed with regards to their technological feasibility and rnanufacturability. In addition, non-standard fabrication process modules for triplegate nanoscale MOSFETs and sub-10 nm nanowires are presented. Alternatives to costly extreme ultraviolet (EUV) lithography are proposed as well as a self-aligned nickel silicide module to reduce inherent parasitic access resistances.
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53.
  • Lemme, Max C., 1970-, et al. (författare)
  • Subthreshold behavior of triple-gate MOSFETs on SOI material
  • 2004
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:4, s. 529-534
  • Tidskriftsartikel (refereegranskat)abstract
    • The fabrication of n-type multi-wire MOSFETs on SOI material with triple-gate structures is presented. The output and transfer characteristics of devices with a gate length of 70 nm and a MESA width of 22 nm demonstrate clearly the suppression of short channel effects (SCE). In addition, these triple-gate structures are compared with planar SOI devices of comparable dimensions. The influence of biasing the substrate (back gate) is analyzed and compared to simulation data.
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54.
  • Lemme, Max C., 1970-, et al. (författare)
  • Subthreshold characteristics of p-type triple-gate MOSFETs
  • 2003
  • Ingår i: ESSDERC 2003. - NEW YORK : IEEE. ; , s. 123-126
  • Konferensbidrag (refereegranskat)abstract
    • The fabrication and characterization of triple-gate p-type metal-oxide semiconductor field effect transistors (p-MOSFETs) on SOI material with multiple channels is described. To demonstrate the beneficial effects of the triple-gate structure on scaling, output and transfer characteristics of 70nm printed gate length p-MOSFETs with 22nm MESA width are presented. The geometrical influence of triple-gate MESA width on subthreshold behavior is investigated in short- and long channel devices. The temperature dependence of subthreshold characteristics is discussed.
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55.
  • Liberis, J., et al. (författare)
  • Hot-phonon temperature and lifetime in biased boron-implanted SiO2/Si/SiO2 channels
  • 2006
  • Ingår i: Semiconductor Science and Technology. - : IOP Publishing. - 0268-1242 .- 1361-6641. ; 21:6, s. 803-807
  • Tidskriftsartikel (refereegranskat)abstract
    • Microwave noise temperature is measured as a function of supplied electric power in 100 nm thick silicon on insulator layers. At 293 K, the estimated hot-hole energy-relaxation time decreases from similar to 9 ps at power below 0.05 nW/hole down to similar to 1.55 ps in the power range (2-10) nW/hole. The results are interpreted in terms of hot-hole interaction with longitudinal optical (LO) phonons. A comparison of the experimental data with those calculated in the hot-hole-temperature approximation indicates accumulation of non-equilibrium optical phonons (termed hot phonons). In the power range of the dominant hole-LO phonon interaction, the increase in equivalent hot-phonon temperature is proportional to the increase in hot-hole temperature. The estimated value for the hot-phonon lifetime, (1.75 +/- 0.4) ps, is comparable with the hot-hole energy-relaxation time at the high bias, similar to 1.55 ps.
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56.
  • Lu, Y., et al. (författare)
  • Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors
  • 2009
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 352-355
  • Tidskriftsartikel (refereegranskat)abstract
    • With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.
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57.
  • Mashoff, T., et al. (författare)
  • Bistability and Oscillatory Motion of Natural Nanomembranes Appearing within Monolayer Graphene on Silicon Dioxide
  • 2010
  • Ingår i: Nano letters (Print). - : American Chemical Society (ACS). - 1530-6984 .- 1530-6992. ; 10:2, s. 461-465
  • Tidskriftsartikel (refereegranskat)abstract
    • The truly two-dimensional material graphene is an ideal candidate for nanoelectromechanics due to its large strength and mobility. Here we show that graphene flakes provide natural nanomembranes of diameter down to 3 nm within its intrinsic rippling. The membranes can be lifted either reversibly or hysteretically by the tip of a scanning tunneling microscope. The clamped-membrane model including van-der-Waals and dielectric forces explains the results quantitatively. AC-fields oscillate the membranes, which might lead to a completely novel approach to controlled quantized oscillations or single atom mass detection.
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58.
  • Nazarov, A. N., et al. (författare)
  • Charge trapping in ultrathin Gd2O3 high-k dielectric
  • 2007
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:9-10, s. 1968-1971
  • Tidskriftsartikel (refereegranskat)abstract
    • Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 x 10(-20) cm(2). The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 x 10(12) eV(-1) cm(-2) near the valence band edge.
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59.
  • Passi, Vikram, et al. (författare)
  • Suspended silicon-on-insulator nanowires for the fabrication of quadruple gate mosfets
  • 2007
  • Ingår i: Nanoscaled Semiconductor-on-Insulator Structures and Devices. - Dordrecht : Springer Netherlands. - 9781402063787 ; , s. 89-94
  • Konferensbidrag (refereegranskat)abstract
    • Scaling of MOSFET physical dimensions is approaching the OF nanoscale regime, which causes increase of short-channel effects such that the electrical performance of classical MOSFET structure is becoming seriously degraded. The limits of silicon scaling have been the major challenge for technologists for the past years. With the 90 nm generation in production and despite many roadblocks, the latest International Roadmap for Semiconductors 2005 expects that CMOS can be scaled down to 16 nm, by introducing new transistor architectures and materials. In this paper, we propose fabrication of a non-classical device architecture namely the "Quadruple-Gate MOSFET" which is based on definition of narrow, suspended silicon fins defined by electron-beam lithography into the top-silicon film of a Silicon-on-Insulator (SOI) wafer.
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60.
  • Peibst, R., et al. (författare)
  • PECVD grown Ge nanocrystals embedded in SiO(2) : From disordered to templated self-organization
  • 2009
  • Ingår i: MICROELECTRONICS JOURNAL. - : Elsevier BV. - 0026-2692. ; 40:4-5, s. 759-761
  • Tidskriftsartikel (refereegranskat)abstract
    • We present a new "templated self-organization" method for the preparation of Ge nanocrystals in SiO(2) that combines a bottom-up with a top-down approach for nanostructuring. Ge nanocrystals are formed by self-organization induced by thermal annealing of thin Ge films embedded ill SiO(2) whose areas are predefined by nanoimprint patterning. Thus Much smaller Structure sizes call be achieved than by pure nanostructuring and touch more regular structures call be prepared than by pure self-organization. in particular, the method enables the generation of Ge nanocrystals of equal size at predefined vertical and lateral positions thus facilitating the fabrication of nanoscaled devices due to the Suppression of Structural fluctuations.
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61.
  • Raeissi, Bahman, 1979, et al. (författare)
  • High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
  • 2007
  • Ingår i: ESSDERC 2007. - 9781424411238 ; , s. 283-286
  • Konferensbidrag (refereegranskat)abstract
    • Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd(2)O(3) prepared by MBE and ALD, and for HfO(2) prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.
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62.
  • Raeissi, Bahman, 1979, et al. (författare)
  • High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy
  • 2008
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 52:9, s. 1274-1279
  • Tidskriftsartikel (refereegranskat)abstract
    • Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 preparedby molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO2 prepared byreactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance.The capture cross sections are found to be thermally activated and to increase steeply with theenergy depth of the interface electron states. The methodology adopted is considered useful for increasingthe understanding of high-k-oxide/silicon interfaces.
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63.
  • Schmidt, M., et al. (författare)
  • Impact of H-2/N-2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks
  • 2005
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 80, s. 70-73
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper reports on the influence of forming gas annealing (5%H-2/95%N-2) over the temperature range 350 degrees C-550 degrees C on the density of electrically active interface states in Si(100)/SiO2/HfO2/TiN gate stacks. Prior to forming gas annealing the distribution of interface states across the energy gap exhibits the electrical signature of the P-b0 dangling bond centre for the hydrogen free Si(100)/SiO2 interface. Forming gas annealing at 350 degrees C and 400 degrees C results in a reduction of the interface state density, with an increase in interface state density for forming gas anneals in the range 450 degrees C-550 degrees C. The effect of the cooling ambient for the forming gas anneal (N-2 or H-2/N-2) is also reported.
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64.
  • Schmidt, M., et al. (författare)
  • Mobility extraction in SOI MOSFETs with sub 1 nm body thickness
  • 2009
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:12, s. 1246-1251
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem, Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in Such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.
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65.
  • Schmidt, M., et al. (författare)
  • Mobility Extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness
  • 2009
  • Ingår i: ULIS 2009. - NEW YORK : IEEE. ; , s. 27-30
  • Konferensbidrag (refereegranskat)abstract
    • In this abstract, the impact of series resistance on mobility extraction in conventional and recessed-gate ultra thin body (UTB) n-MOSFETs is investigated. High series resistance leads to an overestimation of the internal source / drain voltage and influences the measurement of the gate to channel capacitance. A specific MOSFET design that includes additional channel contacts and recessed gate technology are used to successfully extract mobility down to 0.9 nm silicon film thickness (4 atomic layers). Quantum mechanical effects are found to shift the threshold voltage and degrade mobility at these extreme scaling limits.
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66.
  • Schmidt, M., et al. (författare)
  • Nickel-silicide process for ultra-thin-body SOI-MOSFETs
  • 2005
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 82:3-4, s. 497-502
  • Tidskriftsartikel (refereegranskat)abstract
    • A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices.
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67.
  • Vaziri, Sam, et al. (författare)
  • A Hysteresis-Free High-k Dielectric and Contact Resistance Considerations for Graphene Field Effect Transistors
  • 2011
  • Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. ; 41:7, s. 165-171
  • Tidskriftsartikel (refereegranskat)abstract
    • We demonstrate a high-k atomic layer deposition process for graphene field effect transistors which suppresses hysteresis in ambient air measurements. Furthermore, the mobility of the GFETs only degrades by a factor of about two compared to uncovered devices. We further introduce a model that shows the influence of graphene-metal contact resistance at the source and drain on parameter extraction like mobility and transconductance.
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68.
  • Vratzov, B, et al. (författare)
  • Large scale ultraviolet-based nanoimprint lithography
  • 2003
  • Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 21:6, s. 2760-2764
  • Tidskriftsartikel (refereegranskat)abstract
    • Limits in resolution and accuracy of large scale ultraviolet (UV)-based nanoimprint lithography using rigid quartz molds and spin coated UV curable resists are presented. The resolution and precision parameters are closely followed from pattern in the mold through imprints in the resist and finally compared with structures transferred into silicon by special etching processes. Specific attention is paid to the simultaneous patterning of nano and microscale structures. The applicability for functional nanoelectronic components is demonstrated by the fabrication of an NMOS transistor based on SOL whose channel width is reduced to 50 nm. (C) 2003 American Vacuum Society.
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69.
  • Wahlbrink, T., et al. (författare)
  • Highly selective etch process for silicon-on-insulator nano-devices
  • 2005
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 78-79:SI, s. 212-217
  • Tidskriftsartikel (refereegranskat)abstract
    • Reactive ion etch (RIE) processes with HBr/O-2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12 nm gate length and optimized photonic devices with ultrahigh Q-factors.
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70.
  • Wahlbrink, T., et al. (författare)
  • Supercritical drying for high aspect-ratio HSQ nano-structures
  • 2007
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 84:5-8, s. 1045-1048
  • Tidskriftsartikel (refereegranskat)abstract
    • The benefits of supercritical resist drying (SRD) technique using carbon dioxide (CO2) are investigated with respect to the resolution of dense patterns and the aspect ratio (AR) of nano-structures in rather thick HSQ layers. For double lines separated by a distance of 50 nm the maximum achievable AR is trebled using SRD processes compared to conventional nitrogen blow. The mechanical stability of resist structures is significantly improved by using SRI).
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71.
  • Wahlbrink, T., et al. (författare)
  • Supercritical drying process for high aspect-ratio HSQ nano-structures
  • 2006
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 83:4-9, s. 1124-1127
  • Tidskriftsartikel (refereegranskat)abstract
    • Supercritical resist drying allows the fabrication of high aspect-ratio (AR) resist patterns. The potential of this drying technique to increase the maximum achievable AR and the resolution of the overall lithographic process is analyzed for hydrogen silsesquioxane (HSQ). The maximum achievable AR is doubled compared to conventional nitrogen blow drying. Furthermore, the resolution is improved significantly.
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72.
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