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| 4. |
- Hellberg, Lars, et al.
(författare)
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System oriented VLSI curriculum at KTH
- 1997
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Ingår i: ; , s. 57-59
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Konferensbidrag (refereegranskat)abstract
- This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products
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- Hemani, Ahmed, et al.
(författare)
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High-level synthesis of control and memory intensive communication systems
- 1995
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Ingår i: ; , s. 185-191
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level
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- Horn, Wolfgang, et al.
(författare)
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Hardware synthesis of an ATM multiplexer from SDL to VHDL : a case study
- 1999
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Ingår i: VLSI ’99. Proceedings IEEE Computer Society Workshop On. ; , s. 100-105
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Konferensbidrag (refereegranskat)abstract
- Hardware synthesis of SDL models poses several problems, because SDL uses Communicating Sequential Processes (CSP) paradigm for system specification. It allows dynamic processes and its semantics assume an infinite FIFO buffer at the input of each process for inter-process communication. We had presented previously a methodology and later refined it for efficient hardware synthesis from SDL specification. In this paper we describe the experience of applying this methodology to a large case study. The case study is an ATM Multiplexer which exhibits a complex control flow and uses large tables. It was modelled using multiple processes. Hardware synthesis was carried out using the methodology starting from its SDL model. The results show that the methodology leads to a correct and efficient hardware implementation. In particular, the methodology avoids use of costly FIFO buffers for implementing inter-process communication and allows sharing of hardware resources among various instances of the same process. The final implementation also meets the 155 Mbit/sec data rate performance requirement
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| 12. |
- Jantsch, Axel, et al.
(författare)
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The Rugby Model : a conceptual frame for the study of modelling, analysis and synthesis concepts of electronic systems
- 1999
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Ingår i: Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings. ; , s. 256-262
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Konferensbidrag (refereegranskat)abstract
- We propose a conceptual framework, called the Rugby Model, in which designs, design processes and design tools can be studied. It is an extension of the Y chart and adds two dimensions for design representation, namely Data and Tune. The behavioural domain of Y chart is replaced by a more restricted domain called Computation. The structural and physical domains of Y chart are merged into a more general domain called Communication. A fifth dimension deals with design manipulations and transformations at three abstraction levels. The model shall establish a common understanding of modelling and design process concepts for communication and education in the community. In a case study we illustrate how a design can be characterized with the concepts the Rugby model
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| 19. |
- O'Nils, Mattias, et al.
(författare)
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Design of D-AMPS Channel Decoder with Codesign Methodologies
- 1996
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Ingår i: BEC '96, the 5th Biennial Baltic Electronics Conference, October 7-11, 1996, Tallinn, Estonia : proceedings. - Tallinn, Estonia : Tallinn Technical University. - 9789985590263 ; , s. 491-
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Konferensbidrag (refereegranskat)abstract
- This paper is a case study on tool based codesign methodology. The presented methods are observed by applying a D-AMPS channel decoder design to a codesign research tool-kit. The channel decoder functionality is described with five thousand lines of C code. The analysis (profiling, estimation, hardware-software partitioning and verification) of the C description are presented in the paper.
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| 22. |
- Svantesson, Bengt, et al.
(författare)
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A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts
- 1996
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Konferensbidrag (refereegranskat)abstract
- Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: Characterise CMISTs from the synthesis viewpoint; Contend that the synthesis demands of CMISTs can be met within the framework of a general purpose High-level synthesis tool, by making parts of it adaptive to the input, rather than develop a complete tool for a particular type of application; Present an allocation strategy that automatically adapts for CMISTs; Present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; Present the results of applying the synthesis methodology to the OAM as a test case. The results are compared with the result from two commercial High-level synthesis tool; Prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our obtained by designing manually at register-transfer level; The results is also compared with the results from two commercial HLS tools.
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| 26. |
- Tammemäe, Kalle, et al.
(författare)
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AKKA: A Tool-kit for Cosynthesis and Prototyping
- 1996
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Ingår i: Hardware-Software Cosynthesis for Reconfigurable Systems, IEE Colloquium, Bristol 22 Feb. 1996. - : IEE. ; , s. 8/1-8/8
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- Shortened design and life time of embedded systems has motivated active research in HW/SW co-design area, together with evolution of relatively long-life of reconfigurable HW. In this paper we present Akka1[1][2] - a set of tools for design space exploration, co-simulation and co-synthesis with two industrial examples from the telecommunication field - Maintenance functionality of the ATM protocol and Channel decoder functionality of a D-AMPS base station. For fast prototyping we have selected Xilinx XC4013 FPGA based board from Virtual Computer Corporation. The board is connected to the system bus (SBus) of the host computer.
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| 28. |
- Öberg, Johnny, et al.
(författare)
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A rule-based approach for improving allocation of filter structures in HLS
- 1996
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Ingår i: Ninth International Conference on VLSI Design, 1996. Proceedings. - : IEEE conference proceedings. - 0818672285 ; , s. 133-139
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Konferensbidrag (refereegranskat)abstract
- A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool
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