| 1. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Compensation Technique for Two-Stage Differential OTAs
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598
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Tidskriftsartikel (refereegranskat)abstract
- In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
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| 2. |
- Afzal, Nadeem, et al.
(författare)
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Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:9, s. 641-645
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.
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| 3. |
- Andersson, Niklas, et al.
(författare)
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A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:10, s. 773-777
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Tidskriftsartikel (refereegranskat)abstract
- A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.
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| 4. |
- Angelov, Pavel, et al.
(författare)
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A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:11, s. 860-864
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Tidskriftsartikel (refereegranskat)abstract
- We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.
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| 5. |
- Bevilacqua, Andrea, et al.
(författare)
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Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 59:1, s. 20-24
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Tidskriftsartikel (refereegranskat)abstract
- The theoretical phase noise performance of a tuned-input tuned-output (TITO) oscillator is analyzed with a rigorous approach, which yields a compact closed-form phase noise equation that is dependent only on the value of the circuit components and current consumption of the oscillator. A straightforward comparison with the more commonly used differential LC-tank oscillator shows that the latter is in fact superior to the TITO oscillator, at least if the oscillator behavior is not too distant from the ideal behavior considered in the analysis. Phase noise simulations match admirably the theoretical results.
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| 6. |
- Bhide, Ameya, et al.
(författare)
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An 8-GS/s 200-MHz Bandwidth 68-mW ΔΣ DAC in 65-nm CMOS
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 60:7, s. 387-391
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an 8-GS/s 12-bit input ΔΣ digital-to-analog converter (DAC) with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1–1 digital ΔΣ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR, and $-$57-dBc IMD3, with a power consumption of 68 mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
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| 7. |
- Fritzin, Jonas, et al.
(författare)
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Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 59:11, s. 726-730
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents the design and analysis of a 5.5-V class-D stage used in two fully integrated watt-level, +32.0 and +29.7 dBm, outphasing RF power amplifiers (PAs) in standard 130- and 65-nm CMOS technologies. The class-D stage utilizes a cascode configuration, driven by an ac-coupled low-voltage driver, to allow a 5.5-V supply in the 1.2-/2.5-V technologies without excessive device voltage stress. The rms electric fields (E) across the gate oxides and the optimal bias point, where the voltage stress is equally divided between the transistors, are computed. At the optimal bias point, the rms E, the power dissipation of the parasitic drain capacitance of the common-source transistors, and the equivalent on-resistances are reduced by approximately 25%, 50%, and 25%, compared to a conventional cascode (inverter) stage. To the authors best knowledge, the class-D PAs presented are among the first fully integrated CMOS outphasing PAs reaching +30 dBm and demonstrate state-of-the-art output power and bandwidth.
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| 8. |
- Fritzin, Jonas, et al.
(författare)
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Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
- 2011
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 58:10, s. 642-646
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.
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| 9. |
- Garrido Gálvez, Mario, et al.
(författare)
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Accurate Rotations Based on Coefficient Scaling
- 2011
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 58:10, s. 662-666
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents a novel approach for improving the accuracy of rotations implemented by complex multipliers, based on scaling the complex coefficients that define these rotations. A method for obtaining the optimum coefficients that lead to the lowest error is proposed. This approach can be used to get more accurate rotations without increasing the coefficient word length and to reduce the word length without increasing the rotation error. This brief analyzes two different situations where the optimization method can be applied: rotations that can be optimized independently and sets of rotations that require the same scaling. These cases appear in important signal processing algorithms such as the discrete cosine transform and the fast Fourier transform (FFT). Experimental results show that the use of scaling for the coefficients clearly improves the accuracy of the algorithms. For instance, improvements of about 8 dB in the Frobenius norm of the FFT are achieved with respect to using non-scaled coefficients.
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| 10. |
- Garrido Gálvez, Mario, et al.
(författare)
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Optimum Circuits for Bit Reversal
- 2011
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 58:10, s. 657-661
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.
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| 11. |
- Hausmair, Katharina, 1982, et al.
(författare)
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Multiplierless implementation of an aliasing-free digital pulsewidth modulator
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 60:9, s. 592-596
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Tidskriftsartikel (refereegranskat)abstract
- Digital pulsewidth modulators are used to transform nonconstant amplitude signals into pulsed signals, such that the information lying in the signal amplitude is encoded in the widths of pulses. Because of the inherent aliasing distortion in digital pulsewidth-modulated signals, additional signal processing steps are required to make pulsewidth modulation (PWM) suitable for applications like digital audio amplification or burst-mode radio-frequency transmitters. These processing steps, however, entail an undesirable increase in computational effort. This brief presents a multiplierless implementation of a digital aliasing-free pulsewidth modulator using lookup tables, adders, and arithmetic shifts only. Mathematical equations of asymmetric double-edge PWM are given, as well as a modified aliasing-free version of this PWM technique that directly integrates the distortion-avoiding signal processing steps into the pulsewidth modulator. Based on these equations, a multiplierless implementation of the aliasing-free PWM (AF-PWM) is developed. Simulation results obtained with a Simulink fixed-point model show that the proposed modulator implementation provides a feasible solution for realizing AF-PWM with low computational effort.
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| 12. |
- Johansson, Håkan
(författare)
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Fractional-Delay and Supersymmetric Mth-Band Linear-Phase FIR Filters Utilizing Partially Symmetric and Antisymmetric Impulse Responses
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 59:6, s. 366-370
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Tidskriftsartikel (refereegranskat)abstract
- This brief considers fractional-delay finite-length impulse response (FIR) filters and a class of supersymmetric Mth-band linear-phase FIR filters utilizing partially symmetric and partially antisymmetric impulse responses. Design examples reveal significant multiplication savings, depending on the specification, as compared to traditional filters.
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| 13. |
- Mao, Jia, et al.
(författare)
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A Subgigahertz UWB Transmitter With Wireless Clock Harvesting for RF-Powered Applications
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 61:5, s. 314-318
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Tidskriftsartikel (refereegranskat)abstract
- A subgigahertz ultrawideband (UWB) transmitter (TX) with wireless clock harvesting is presented for RF-powered applications such as RF identifications and implantable devices in the 180-nm CMOS process. The proposed low-power TX consists of a harmonic injection-locked ring oscillator (ILRO), a synchronized pulse generator, and a driver stage. Through wireless injection locking, a 450-MHz carrier is extracted using the sub-harmonic of an ultrahigh frequency signal radiated by a reader. Following the ILRO, the carrier is gated and amplified to generate the UWB pulses. This approach avoids power-hungry frequency synthesis circuitry and bulky crystal reference, and it relaxes the timing synchronization between the reader and the tag. Due to aggressive duty cycling and the fast setup time (< 50 ns at an input power of -15 dBm), the proposed TX is power scalable with an energy consumption of 35 pJ/pulse. To comply with the Federal Communications Commission regulations, the maximum pulse rate is up to 5 MHz with a peak-to-peak pulse amplitude of 0.75 V and a corresponding power consumption of 175 mu W, which is favorable to RF-powered applications.
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| 14. |
- Rabén, Hans, et al.
(författare)
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A model for MOS diodes with vth-cancellation in RFID rectifiers
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 59:11, s. 761-765
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Tidskriftsartikel (refereegranskat)abstract
- A theoretical model for diode-connected MOS transistors with a threshold cancellation technique is developed. The model is based on a detailed analysis of the technique with internal threshold cancellation (ITC) and reveals design insight and performance limitations. Derived design equations illustrate the tradeoff between the voltage drop and the reverse leakage of the diode. Furthermore, a design procedure for the optimization of the power conversion efficiency (PCE) of a bridge rectifier with ITC MOS diodes was developed based on the model. A rectifier was designed and implemented in an austriamicrosystems 0.35-$muhbox{m}$ CMOS process, and Cadence simulation results of the PCE and the voltage conversion efficiency show good agreement with the model.
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| 15. |
- Sheikh, Zaka Ullah, et al.
(författare)
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Linear Programming Design of Coefficient Decimation FIR Filters
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - 1549-7747 .- 1558-3791. ; 59:1, s. 60-64
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Tidskriftsartikel (refereegranskat)abstract
- The coefficient decimation technique for reconfigurable FIR filters was recently proposed as a filter structure with low computational complexity. In this brief, we propose to design these filters using linear programming taking all configuration modes into account, instead of only considering the initial reconfiguration mode as in previous works. Minimax solutions with significantly lower approximation errors compared to the straightforward design method in earlier works are obtained. In addition, some new insights that are useful when designing coefficient decimation filters are provided.
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| 16. |
- Sjöblom, Peter, et al.
(författare)
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Constant Mismatch Loss Boundary Circles and Their Application to Optimum State Distribution in Adaptive Matching Networks
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:12, s. 922-926
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Tidskriftsartikel (refereegranskat)abstract
- An adaptive matching network provides a number of states between which it can be reconfigured. At a certain frequency, the matching network transforms a reference impedance to different impedances for the different states. The circuit will be able to match those impedances perfectly to the reference impedance, and impedances close to those will also be fairly well matched. The matching will, however, decline for impedances further away and eventually become too low. By defining the level of acceptable matching, a boundary can be formed that identifies an area of impedances that are matched well enough. In the same manner, a boundary is possible to form for constant mismatch loss. It is shown that the boundaries are circular if plotted in a Smith chart and that the sizes of the circles depend on the location of $z_{L}$. With these results, it is then investigated how the impedances should be distributed to minimize the number of states while still achieving the matching performance and coverage.
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| 17. |
- ud Din, Imad, et al.
(författare)
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Wideband SAW-Less Receiver Front-End with Harmonic Rejection Mixer in 65-nm CMOS
- 2013
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 60:5, s. 242-246
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Tidskriftsartikel (refereegranskat)abstract
- A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S11 below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.
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| 18. |
- Winstead, Chris, et al.
(författare)
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Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 59:12, s. 913-917
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Tidskriftsartikel (refereegranskat)abstract
- echniques are evaluated for implementing error- correction codes (ECC) in wireless applications with severe power constraints, such as bio-implantable devices and energy harvesting motes. Standard CMOS architectures are surveyed and compared against alternative implementations, including known sub-VT analog decoding techniques. Novel sub-VT digital designs are proposed and their power efficiency is evaluated as a function of operating voltage and clock frequency. Sub- VT implementation is predicted to offer 29× gain in power consumption for a (3,6) LDPC decoder of length N = 512 operating at a throughput of 200Mbps, compared to standard digital implementation of the same design.
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| 19. |
- Zhang, Dai, et al.
(författare)
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Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE. - 1549-7747 .- 1558-3791. ; 61:9, s. 666-670
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Tidskriftsartikel (refereegranskat)abstract
- This brief analyzes the effect of capacitor variation on the design of high-resolution nonbinary-weighted successive-approximation-register analog-to-digital converters in terms of radix, conversion steps, and accuracy. Moreover, the limitation caused by the one-side redundancy of the nonbinary-weighted network is addressed and a corresponding solution with a mathematical derivation is provided. In order to relax the mismatch requirement on the capacitor sizing while still ensuring enough linearity, a bottom-up weight calibration technique accounting for noise and offset errors is proposed, and its effectiveness is demonstrated. This calibration approach can be easily incorporated into a charge-redistribution converter without modifying its main architecture and conversion sequence.
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| 20. |
- ÖZEN, MUSTAFA, 1984, et al.
(författare)
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Continuous Class-E Power Amplifier Modes
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 59:11, s. 731-735
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, a continuum of novel closed-form solutions is derived for class-E power amplifiers (PAs). It is analytically proven that the class-E zero voltage/zero voltage derivative switching conditions can be satisfied for an arbitrarily selected reactive second harmonic switch impedance (Z 2 S ). The higher order harmonic currents are terminated capacitively. The conventional class-E, class- E/F 2 , and class-EF 2 modes are thus subsets of the continuum. The arbitrary selection of Z 2 S enables robust waveform engineering for performance optimization in specific applications. Furthermore, the theoretical derivation provides important possibilities for wideband class-E PA synthesis. © 2004-2012 IEEE.
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