| 1. |
- Akhlaghpasand, Hossein, et al.
(författare)
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Jamming Suppression in Massive MIMO Systems
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 67:1, s. 182-186
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we propose a framework for protecting the uplink transmission of a massive multiple-input multiple-output (mMIMO) system from a jamming attack. Our framework includes a novel minimum mean-squared error-based jamming suppression (MMSE-JS) estimator for channel training and a linear zero-forcing jamming suppression (ZFJS) detector for uplink combining. The MMSE-JS exploits some intentionally unused pilots to reduce the pilot contamination caused by the jammer. The ZFJS suppresses the jamming interference during the detection of the legitimate users' data symbols. The proposed framework is implementable, since the complexities of computing the MMSE-JS and the ZFJS are linear (not exponential) with respect to the number of antennas at the base station and can be fabricated using 28-nm fully depleted silicon on insulator technology and for the mMIMO systems. Our analysis shows that the jammer cannot dramatically affect the performance of an mMIMO system equipped with the combination of MMSE-JS and ZFJS. Numerical results confirm our analysis.
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| 2. |
- Andreani, Pietro
(författare)
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Some Results on Oscillation Stability in Multi-Mode Harmonic Oscillators
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:3, s. 860-864
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Tidskriftsartikel (refereegranskat)abstract
- We study the stability of oscillation in two different multi-mode harmonic oscillators by means of Barkhausen’s criterion, involving a minimum of mathematical machinery in favor of a more intuitive, circuit-based approach. The results of the theoretical analysis match very closely those obtained through transient simulations, confirming occasionally surprising outcomes of the latter.
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| 3. |
- Behmanesh, Baktash, et al.
(författare)
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On the Calculation and Simulation of Loop Gain in Feedback Circuits
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:11, s. 4033-4037
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Tidskriftsartikel (refereegranskat)abstract
- We derive the expression of the loop gain in a circuit containing one or more feedback loops, where the transfer functions building the expression are found by means of a few AC analyses on the circuit. No approximations or assumptions on the nature of the loop or of the impedances therein contained are necessary. While hand calculations are certainly possible in the case of simpler circuits, the method is especially suitable for deployment in an analog circuit simulator environment.
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| 4. |
- Castañeda, Oscar, et al.
(författare)
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High-Bandwidth Spatial Equalization for mmWave Massive MU-MIMO with Processing-in-Memory
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747 .- 1558-3791. ; 67:5, s. 891-895
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Tidskriftsartikel (refereegranskat)abstract
- All-digital basestation (BS) architectures enable superior spectral efficiency compared to hybrid solutions in massive multi-user MIMO systems. However, supporting large bandwidths with all-digital architectures at mmWave frequencies is challenging as traditional baseband processing would result in excessively high power consumption and large silicon area. The recently-proposed concept of finite-alphabet equalization is able to address both of these issues by using equalization matrices that contain low-resolution entries to lower the power and complexity of high-throughput matrix-vector products in hardware. In this brief, we explore two different finite-alphabet equalization hardware implementations that tightly integrate the memory and processing elements: (i) a parallel array of multiply-accumulate (MAC) units and (ii) a bit-serial processing-in-memory (PIM) architecture. Our all-digital VLSI implementation results in 28nm CMOS show that the bit-serial PIM architecture reduces the area and power consumption up to a factor of 2× and 3×, respectively, when compared to a parallel MAC array that operates at the same throughput.
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| 5. |
- Chen, Hui, et al.
(författare)
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Hyperbolic CORDIC-Based Architecture for Computing Logarithm and Its Implementation
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 67:11, s. 2652-2656
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Tidskriftsartikel (refereegranskat)abstract
- We present a CORDIC (Coordinate Rotation Digital Computer)-based method to compute the logarithm function with base 2 and validate this method by software simulation and hardware implementation. Technically, we overcome the limitation of traditional hyperbolic CORDIC and transform it based on the idea of generalized hyperbolic CORDIC so that it can be used to compute $log_{2}x\;(x\;\epsilon \;[1,2))$ . The proposed method requires only simple shift-and-add operations and has a great tradeoff between precision (or speed) and area. In MATLAB, we provide different precisions corresponding to the iterations of the transformed CORDIC for user needs. Using a pipelined structure and setting the number of iterations to be 16 (the average relative error is $2.09\times 10<^>{-6}$ ), we implement an example hardware circuit. Synthesized under the SMIC 65nm CMOS technology, the circuit has an area of 24100 $\mu m<^>{2}$ and computation time of 11.1 ns, which can save 31.04x0025; area and improve 6.92x0025; computation speed averagely compared with existing methods.
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| 6. |
- Deng, Mingxin, et al.
(författare)
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Efficient Parallel Polynomial-Based Compensation Structure for Frequency Response Mismatch in Two-Channel TI-ADCs
- 2024
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 71:2, s. 992-996
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Tidskriftsartikel (refereegranskat)abstract
- This brief introduces a compensation structure for frequency response mismatch (FRM) errors in two-channel time-interleaved analog-to-digital converters (TI-ADCs) based on polynomial models of the channel frequency responses. It can be used for any Nyquist band and it comprises parallel error approximation branches (EABs), each branch consisting of a fixed differentiator of unique degree cascaded with a variable multiplier and a simple modulator. It suffices to alter the variable multipliers when the channels change, thereby avoiding online filter design. In addition, it achieves a lower latency and a significantly lower computational complexity compared to cascaded polynomial-based structures. Numerical simulations and comparisons are included, validating the efficacy of the proposed structure.
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| 7. |
- Fernandez-Prieto, Armando, et al.
(författare)
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Glide Symmetry Applied to the Design of Common-Mode Rejection Filters Based on Complementary Split-Ring Resonators
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 70:6, s. 1911-1915
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, glide symmetry is applied to design common-mode rejection filters based on defected ground structures with bandstop response. To this aim, complementary split-ring resonators are chosen as the basic components for common-mode rejection. To illustrate the advantages of using glide symmetry, three implementations are studied and compared. The results reveal that glide symmetry offers the best performance in terms of common-mode rejection level and fractional bandwidth. Furthermore, glide symmetry barely affects the integrity of the differential mode. A prototype of each of the considered symmetries has been designed, simulated, and tested for practical validation. Good agreement is observed between the simulated and measured results, experimentally demonstrating the advantages of glide symmetry.
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| 8. |
- Horestani, Fatemeh Karami, et al.
(författare)
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Ultra-High-Resistance Pseudo-Resistors with Small Variations in a Wide Symmetrical Input Voltage Swing
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE. - 1549-7747 .- 1558-3791. ; 70:8, s. 2794-2798
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a new strategy and circuit configuration composed of serially-connected PMOS devices operating in the subthreshold region for implementing ultra-highvalue resistors required in very low-frequency active-RC filters and bio-amplifiers. Depending on the application, signal bandwidth for instance in bio-amplifiers may vary from a few mHz up to a maximum of 10 kHz. Three different resistor structures are proposed to achieve ultra-high resistance. While ranging in the order of several TY, the proposed ultra-high-resistance pseudoresistors occupy a small on-chip silicon area, which is one of the main issues in the design of analog front-end circuits in ultra-low power implantable biomedical microsystems. In addition, these ultra-high-value resistors lead to the use of a small capacitance to create a very small cut-off frequency. Therefore, the large area to implement capacitances is also considerably reduced. The proposed resistor structures have very small variations about 7% and 12% in a wide input voltage range (-0.5 V +0.5 V), thus significantly improving the total harmonic distortion of bioamplifiers and the analog front-end of the system. Simulation results of different circuits designed in a 180nm CMOS technology, are shown to demonstrate the advantages of the proposed ultra-high-resistance pseudo-resistors.
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| 9. |
- Huang, Yu-Kai, et al.
(författare)
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A Current Monitoring and Over-Current Detection Circuit for Safe Electrical Stimulation
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 70:5, s. 1684-1688
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an integrated solution to over-current protection in neuromuscular stimulators. The proposed approach provides fast detection of a single-fault condition, i.e., unintentional electrode short circuit or malfunction of the stimulator, thereby preventing prolonged high-intensity currents from flowing into tissues. In addition, a programmable current threshold enables the system to be also used for monitoring the stimulation intensity. The proposed solution was designed in a 180 nm high-voltage CMOS technology, and its functionality was verified by post-layout simulations in which the safety mechanisms were tested under fault conditions. The implementation only occupies an area of 0.286 mm2, making it feasible to be embedded in fully integrated NMES stimulators while providing the required patient safety.
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| 10. |
- Liu, Xiangyu, et al.
(författare)
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Correlation-Based Calibration for Nonlinearity Mismatches in Dual-Channel TIADCs
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 67:3, s. 585-589
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Tidskriftsartikel (refereegranskat)abstract
- Mismatches affect the dynamic performance of time-interleaved analog-to-digital converters (TIADCs). Linear mismatches can be calibrated by many mature methods, but if higher performance is required, nonlinearity mismatches have to be suppressed. The background calibration method based on input-free band (IFB) functions poorly for narrow-band signals. This brief proposes a correlation-based calibration method for nonlinearity mismatches in dual-channel TIADCs which behaves well for both wide-band and narrow-band signals. The output samples are calibrated by reducing the residual distortions which are approximated by multiplying the pseudo distortions and the estimated mismatch coefficients. The pseudo distortions are acquired by using a frequency-shifter, a differentiator, and multipliers. The coefficients which indicate the mismatch strength are estimated by eliminating the cross-correlation of the calibrated output samples and the calibrated pseudo distortions at zero lag. Simulations show that the proposed method can improve the SFDR by dozens of dBc for narrow-band input signals, compared with the IFB method. For the 16-QAM signal, the error vector magnitude improvement over the IFB method is 35.48 dB.
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| 11. |
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| 12. |
- Qin, Zidi, et al.
(författare)
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A Novel Approximation Methodology and Its Efficient VLSI Implementation for the Sigmoid Function
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 67:12, s. 3422-3426
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, a novel approximation method and its optimized hardware implementation are proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on piecewise approximation and truncated Taylor series expansion, the proposed method achieves very good approximation with low complexity while exploiting data representation with powers of two. In addition, by analyzing gradients of the sigmoid function, a small trick is introduced to improve the approximation precision. Furthermore, to reduce the hardware complexity and shorten the critical path, sampled values of the function are generated with simple logical-mapping. It is shown that the proposed approximation schemes can be implemented with purely combinational logic and the sigmoid function can be computed in one clock cycle. The experimental results demonstrate that the mean absolute errors are at the order of 1 x 10(-3). Compared with prior arts, the new design can obtain significant improvement in critical path with comparable performance.
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| 13. |
- Xu, J., et al.
(författare)
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A Memory-Efficient CNN Accelerator Using Segmented Logarithmic Quantization and Multi-Cluster Architecture
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 68:6, s. 2142-2146
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a memory-efficient CNN accelerator design for resource-constrained devices in Internet of Things (IoT) and autonomous systems. A segmented logarithmic (SegLog) quantization method is exploited to mitigate the on-chip memory and bandwidth requirements, thus accommodating more processing elements (PEs) in a given chip area to organize a reconfigurable multi-cluster architecture. Such algorithm-architecture joint optimization improves the utilization and efficiency of memory resources. SegLog quantization adopting mixed bases optimizes fixed-points placement in different segmentations and improves network accuracy at low-precision representation, while the multi-cluster architecture can reorganize PEs to adapt to various CNN models for efficient dataflow and multi-level data reuse. The evaluation results show that SegLog quantization can achieve 6.4× model compression with 1.73%, 0.74%, 2.11%, and 1.76% accuracy penalty on AlexNet, VGG16, ResNet34, and DenseNet161, respectively. An ASIC implementation with 168 PEs configuration is validated in a 40-nm CMOS process, with 2.54 TOPs/W energy efficiency and 0.8 mm chip area reported. The accelerator has also been implemented on FPGA with 1512 PEs configured and 468 kB on-chip memory thanks to the extensibility of the architecture. It delivers up to 604.8 GOPs performance at 200 MHz, corresponding to a 1.29 GOPs/kB memory efficiency. Compared with the state-of-the-art accelerators, our ASIC implementation enhances area efficiency and arithmetic intensity by 1.94× and 5.62×, while the FPGA implementation achieves the memory efficiency improvement by a factor of 2.34×. IEEE
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| 14. |
- Xu, Jiawei, et al.
(författare)
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Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning
- 2024
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 71:2, s. 627-631
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Tidskriftsartikel (refereegranskat)abstract
- Evaluating the computational accuracy of Spiking Neural Network (SNN) implemented as in-situ learning on large-scale memristor crossbars remains a challenge due to the lack of a versatile model for the variations in non-ideal memristors. This brief proposes a novel behavioral variation model along with a four-stage pipeline for physical memristors. The proposed variation model combines both absolute and relative variations. Therefore, it can better characterize different memristor cycle-to-cycle (C2C) variations in practice. The proposed variation model has been used to simulate the behavior of two physical memristors. Adopting the non-ideal memristor model, the trace-based spiking-timing dependent plasticity (STDP) unsupervised in-memristor learning system is simulated. Although the synaptic-level weight simulation shows a performance degradation of 7.99% and 4.07% increase in the relative root mean square error (RRMSE), the network-level simulation results show no accuracy loss on the MNIST benchmark. Furthermore, the impacts of absolute and relative C2C variations on network performance are simulated and analyzed through two sets of univariate experiments.
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| 15. |
- Yang, Bo, et al.
(författare)
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Optimizing Robustness of Core-Periphery Structure in Complex Networks
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 68:12, s. 3572-3576
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Tidskriftsartikel (refereegranskat)abstract
- Complex networks can be considered as abstractions of complex systems existing in the real world. The potential functionality of networks is related to mesoscale structures in networks, among which the representative ones are community structure and core-periphery (CP) structure. Since many real-world networks will inevitably be attacked, it is of great significance to enhance robustness of networks. However, few of the existing studies about robustness have laid emphasis on robustness of CP structure. In this brief, we first propose a new index to measure the ability of CP structure to resist attacks or errors. Several efficient algorithms based on this index are then devised to maximize robustness of CP structure under reasonable constraint. Numerical results show that the robustness of the CP structure of several representative real-world networks is markedly enhanced. The structural changes in the optimized networks under study and their implication are also discussed.
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| 16. |
- Yu, Yang, et al.
(författare)
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Can Deep Learning Break a True Random Number Generator?
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 68:5, s. 1710-1714
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Tidskriftsartikel (refereegranskat)abstract
- True Random Number Generators (TRNGs) create a hardware-based, non-deterministic noise that is used for generating keys, initialization vectors, and nonces in a variety of applications requiring cryptographic protection. A compromised TRNG may lead to a system-wide loss of security. In this brief, we show that an attack combining power analysis with bitstream modification is capable of classifying the output bits of a TRNG implemented in FPGAs from a single power measurement. We demonstrate the attack on the example of an open source AIS-20/31 compliant ring oscillator-based TRNG implemented in Xilinx Artix-7 28nm FPGAs. The combined attack opens a new attack vector which makes possible what is not achievable with pure bitstream modification or side-channel analysis.
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