| 1. |
- Anderson, John B, et al.
(författare)
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Faster-Than-Nyquist Signaling
- 2013
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Ingår i: Proceedings of the IEEE. - 0018-9219. ; 101:8, s. 1817-1830
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we survey Faster-than-Nyquist (FTN) signaling, an extension of ordinary linear modulation in which the usual data bearing pulses are simply sent faster, and consequently are no longer orthogonal. Far from a disadvantage, this innovation can transmit up to twice the bits as ordinary modulation at the same bit energy, spectrum, and error rate. The method is directly applicable to orthogonal frequency division multiplex (OFDM) and quadrature amplitude modulation (QAM) signaling. Performance results for a number of practical systems are presented. FTN signaling raises a number of basic issues in communication theory and practice. The Shannon capacity of the signals is considerably higher.
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| 2. |
- Dasalukunte, Deepak, et al.
(författare)
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Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems
- 2011
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Ingår i: [Host publication title missing]. - 2159-3477. ; , s. 359-360
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Konferensbidrag (refereegranskat)abstract
- Abstract in UndeterminedFaster-than-Nyquist (FTN) signaling is a method of improving bandwidth efficiency by transmitting information beyond Nyquist's orthogonality limit for interference free transmission. Previously have theoretically established that FTN can provide improved bandwidth efficiency. However, this comes at the cost of higher decoding complexity at the receiver. Our work has evaluated multicarrier FTN signaling for its implementation feasibility and complexity overhead compared to the gains in bandwidth efficiency. The work carried out in this research project includes a systems perspective evaluating performance, algorithm hardware tradeoffs and a hardware architecture leading to a silicon implementation of the decoder for FTN signaling. From the systems perspective, co-existence of FTN and OFDM based multicarrier system has been evaluated. OFDM being a part of many existing and upcoming broadband access technologies such as WLAN, LTE, DVB, this analogy is motivated. On the hardware aspect, the proposed architecture can accommodate both OFDM and FTN systems. The processing blocks in transmitter and receiver were designed for reuse and carry out different functions in the transceiver. Furthemore, the hardware could be configured to operate at varying bandwidth efficiencies (by FTN signaling) to exploit the channel conditions. The decoder implementation also considered block sizes and data rates to comply with the 3GPP standard. The decoding is carried out in as few as 8 iterations making it more practical for implementation in power constrained mobile devices. The decoder is implemented in 65nm CMOS process and occupies a total chip area of 0.8mm2.
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| 3. |
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| 4. |
- Kamuf, Matthias, et al.
(författare)
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Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
- 2010
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Ingår i: Microprocessors and Microsystems. - : Elsevier BV. - 0141-9331. ; 34:2010, s. 129-137
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Tidskriftsartikel (refereegranskat)abstract
- This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
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| 5. |
- Meraji, Reza, et al.
(författare)
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A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
- 2013
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Ingår i: 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS). - 9781479924523 ; , s. 349-352
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Konferensbidrag (refereegranskat)abstract
- Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver.
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| 6. |
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| 7. |
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| 8. |
- Meraji, Reza, et al.
(författare)
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An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- 2011
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Ingår i: [Host publication title missing]. - 2158-1525 .- 0271-4310. - 9781424494736 ; , s. 2881-2884
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Konferensbidrag (refereegranskat)abstract
- A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s.
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| 9. |
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| 10. |
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| 11. |
- Meraji, Reza, et al.
(författare)
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Low power analog channel decoder in sub-threshold 65nm CMOS
- 2010
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Konferensbidrag (övrigt vetenskapligt/konstnärligt)abstract
- This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI’s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW.
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| 12. |
- Meraji, Reza, et al.
(författare)
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Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
- 2011
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Ingår i: [Host publication title missing]. - 9781457705144 ; , s. 1-4
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Konferensbidrag (refereegranskat)abstract
- Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology.
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| 13. |
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| 14. |
- Sjöland, Henrik, et al.
(författare)
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Ultra low power transceivers for wireless sensors and body area networks
- 2014
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Ingår i: 2014 8th International Symposium on Medical Information and Communication Technology (ISMICT). - 2326-828X. - 9781479948567
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Konferensbidrag (refereegranskat)abstract
- A transceiver suitable for devices in wireless body area networks is presented. Stringent requirements are imposed by the high link loss between opposite sides of the body, about 85 dB in the 2.45 GHz ISM band. Despite this, minimum physical size and power consumption are required, and we target a transceiver with 1 mm2 chip area, 1 mW active power consumption, and data rate 250 kbit/s. The receiver is fully integrated., fabricated and measured in 65-nm CMOS, and size and power consumption are carefully considered at all levels of circuit and system design. The modulation is frequency shift keying, chosen because transmitters can be realized with high efficiency and low spurious emissions; a modulation index 2 creates a midchannel spectral notch. A direct-conversion receiver achieves minimum power consumption. A tailored demodulation structure makes the digital baseband compact and low power. The channel decoder has been implemented in both analog and digital domains to find the most power efficient solution. Antenna design and wave propagation are studied via simulations with phantoms. The 2.45 GHz ISM band was chosen as a good compromise between antenna size and link loss. An ultra-low power medium access scheme based on a duty-cycled wake-up receiver is designed.
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