| 1. |
- Mikhaylov, Aleksey I., et al.
(författare)
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On the ion implantation of phosphorus as a method for the passivation of states at the interface between 4H-SiC and SiO2 produced by thermal oxidation in dry oxygen
- 2014
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Ingår i: Semiconductors (Woodbury, N.Y.). - : Maik Nauka-Interperiodica Publishing. - 1063-7826 .- 1090-6479. ; 48:12, s. 1581-1585
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Tidskriftsartikel (refereegranskat)abstract
- A method is suggested for reducing the density of surface states at the 4H-SiC/SiO2 interface by the implantation of phosphorus ions into a 4H-SiC epitaxial layer immediately before the growth of a gate insulator in an atmosphere of dry oxygen. A significant decrease in the density of surface states is observed at a phosphor-ion concentration at the SiO2/SiC interface exceeding 1018 cm−3. However, together with the passivation of surface states, the introduction of phosphorus ions leads to an increase in the built-in charge in the insulator and also slightly deteriorates the reliability of the gate insulator fabricated by this technique.
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| 2. |
- Ghandi, Reza, et al.
(författare)
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Surface-passivation effects on the performance of 4H-SiC BJTs
- 2011
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383 .- 1557-9646. ; 58, s. 259-265
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.
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| 3. |
- Hertel, Stefan, et al.
(författare)
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Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics
- 2012
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Ingår i: Nature Communications. - : Springer Science and Business Media LLC. - 2041-1723. ; 3
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Tidskriftsartikel (refereegranskat)abstract
- Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10 4 and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.
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| 4. |
- Lorenzzi, Jean, et al.
(författare)
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3C-SiC MOS based devices : from material growth to device characterization
- 2011
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Ingår i: Silicon carbide and related materials 2010. - : Trans Tech Publications, Ltd.. ; , s. 433-
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Konferensbidrag (refereegranskat)abstract
- In this work we report on the growth and preparation of 3C-SiC(111) material for metal-oxide-semiconductor (MOS) application. In order to achieve reasonable material quality to prepare MOS capacitors several and crucial steps are needed: 1) heteroepitaxial growth of high quality 3C-SiC(111) layer by vapour-liquid-solid mechanism on 6H-SiC(0001) substrate, 2) surface polishing, 3) homoepitaxial re-growth by chemical vapour deposition and 4) use of an advanced oxidation process combining plasma enhanced chemical vapour deposition (PECVD) SiO2 and short post-oxidation steps in wet oxygen. Combining all these processes the interface traps density (D-it)can be drastically decreased down to 1.2 x 10(10) eV(-1)cm(-2) at 0.63 eV below the conduction band. To our knowledge, these values are the best ever reported for SiC material in general and 3C-SiC in particular.
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| 5. |
- Mikhaylov, Aleksey I., et al.
(författare)
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Alternative method of interface traps passivation by introducing of thin silicon nitride layer at 4H-SiC/SiO2 interface
- 2014
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Ingår i: Materials Research Society Symposium Proceedings. - : Springer Science and Business Media LLC.
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Konferensbidrag (refereegranskat)abstract
- An alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).
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| 6. |
- Roensch, Sebastian, et al.
(författare)
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Drain-current deep level transient spectroscopy investigation on epitaxial graphene/6H-SiC field effect transistors
- 2014
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Ingår i: Mater. Sci. Forum. - 9783038350101 ; , s. 436-439
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Konferensbidrag (refereegranskat)abstract
- The electrically active deep levels in a graphene/silicon carbide field effect transistor (FET) were investigated by drain-current deep level transient spectroscopy (ID-DLTS). An evaluation procedure for ID-DLTS is developed in order to obtain the activation energy, the capture cross section and the trap concentration. We observed three defect centers corresponding to the intrinsic defects E1/E2, Ei and Z1/Z2 in n-type 6H-SiC. The determined parameters have been verified by conventional capacitance DLTS.
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| 7. |
- Sledziewski, Tomasz, et al.
(författare)
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Reduction of density of 4H-SiC/SiO2 interface traps by pre-oxidation phosphorus implantation
- 2014
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Ingår i: Materials Science Forum. - 9783038350101 ; , s. 575-578
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Konferensbidrag (refereegranskat)abstract
- The effect of phosphorus (P) on the electrical properties of the 4H-SiC/SiO2 interface was investigated. Phosphorus was introduced by surface-near ion implantation with varying ion energy and dose prior to thermal oxidation. Secondary ion mass spectrometry revealed that only part of the implanted P followed the oxidation front to the interface. A negative flatband shift due to residual P in the oxide was found from C-V measurements. Conductance method measurements revealed a significant reduction of density of interface traps Dit with energy EC-Eit > 0.3 V for P+-implanted samples with [P]interface = 1.5 · 1018 cm-3 in the SiC layer at the interface. .
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| 8. |
- Yen, Cheng Tyng, et al.
(författare)
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Comparative study of 4H-SiC DMOSFETs with N2O thermal oxide and deposited oxide with post oxidation anneal
- 2014
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Ingår i: Materials Science Forum. - 9783038350101 ; , s. 989-992
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Konferensbidrag (refereegranskat)abstract
- Two kinds of gate oxides, direct thermal oxidation in a nitrous oxide ambient at 1250°C (TGO) and a PECVD oxide followed by a post deposition oxidation in nitrous oxide ambient at 1150°C (DGO) were studied. DGO showed a lower interface trap density and was able to provide a higher current as being implemented in MOSFETs through the improved channel mobility. However the 6.45 MV/cm average breakdown field of DGO is lower than the 10.1 MV/cm breakdown field of TGO. The lower breakdown field, more leaky behavior and the existence of multiple breakdown mechanisms suggest that DGO needs further improvements before it can be used in real applications.
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| 9. |
- Yen, Cheng Tyng, et al.
(författare)
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SiC epi-channel lateral MOSFETs
- 2014
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Ingår i: Materials Science Forum. - 9783038350101 ; , s. 927-930
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Konferensbidrag (refereegranskat)abstract
- SiC lateral MOSFETs with multi-layered epi-channels were studied in this work. The epi-channel consisting of a high concentration n-type epilayer sandwiched between two lightly doped p-type layers showed a maximum field effect mobility of 17 cm2/V.s, as compared to 1.53 cm2/V.s for inversion type devices without epi-channels. These devices are normally-off with an average threshold voltage of 1.34V.
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