| 1. |
- Bao, Yan, et al.
(författare)
-
An Implementation of Cache-Coherence for the Nios II ™ Soft-core processor
- 2009
-
Konferensbidrag (refereegranskat)abstract
- Soft-core programmable processors mapped onto fieldprogrammable gate arrays (FPGA) can be considered as equivalents to a microcontroller. They combine central processing units (CPUs), caches, memories, and peripherals on a single chip. Soft-cores processors represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are parameterized to support application-specific customization. However, these softcore processors are designed to be used in uniprocessor system, not for multiprocessor system. This project describes an implementation to solve the cache coherency problem in an ALTERA Nios II soft-core multiprocessor system.
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| 2. |
- Brorsson, Mats, 1962-, et al.
(författare)
-
Adaptive and flexible dictionary code compression for embedded applications
- 2006
-
Ingår i: Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems. - New York, NY, USA : ACM. - 1595935436 ; , s. 113-124
-
Konferensbidrag (refereegranskat)abstract
- Dictionary code compression is a technique where long instructions in the memory are replaced with shorter code words used as index in a table to look up the original instructions. We present a new view of dictionary code compression for moderately high-performance processors for embedded applications. Previous work with dictionary code compression has shown decent performance and energy savings results which we verify with our own measurement that are more thorough than previously published. We also augment previous work with a more thorough analysis on the effects of cache and line size changes. In addition, we introduce the concept of aggregated profiling to allow for two or more programs to share the same dictionary contents. Finally, we also introduce dynamic dictionaries where the dictionary contents is considered to be part of the context of a process and show that the performance overhead of reloading the dictionary contents on a context switch is negligible while on the same time we can save considerable energy with a more specialized dictionary contents.
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| 3. |
- Fang, Huan, et al.
(författare)
-
Scalable directory architecture for distributed shared memory chip multiprocessors
- 2008
-
Ingår i: Proceedings of the 1st Swedish Workshop on Multi-core Computing. ; , s. 73-81
-
Konferensbidrag (refereegranskat)abstract
- Traditional Directory-based cache coherence protocol is far from optimal for large-scale cache coherent shared memory multiprocessors due to the increasing latency to access directories stored in DRAM memory. Instead of keeping directories in main memory, we consider distributing the directory together with L2 cache across all nodes on a Chip Multiprocessor. Each node contains a processing unit, a private L1 cache, a slice of L2 cache, memory controller and a router. Both L2 cache and memories are distributed shared and interleaved by a subset of memory address bits. All nodes are interconnected through a low latency two dimensional Mesh network.Directory, as a split component as L2 cache, only stores sharing information for blocks while L2 cache only stores data blocks exclusive with L1 cache. Shared L2 cache can increase total effective cache capacity on chip, but also increase the miss latency when data is on a remote node. Being different from Directory Cache structure, our proposal totally removes the directory from memory which saves memory space and reduces access latency. Compared to L2 cache which combines directory information internally, our split L2 cache structure saves over 88% cache space while having achieved similar performance.
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| 4. |
- Fang, Huan, et al.
(författare)
-
Scalable directory architecture for distributed shared memory chip multiprocessors
- 2008
-
Ingår i: SIGARCH Computer Architecture News. - : ACM Press. - 0163-5964 .- 1943-5851. ; 36:5, s. 56-64
-
Tidskriftsartikel (refereegranskat)abstract
- Traditional Directory-based cache coherence protocol is far from optimal for large-scale cache coherent shared memory multiprocessors due to the increasing latency to access directories stored in DRAM memory. Instead of keeping directories in main memory, we consider distributing the directory together with L2 cache across all nodes on a Chip Multiprocessor. Each node contains a processing unit, a private L1 cache, a slice of L2 cache, memory controller and a router. Both L2 cache and memories are distributed shared and interleaved by a subset of memory address bits. All nodes are interconnected through a low latency two dimensional Mesh network. Directory, being a split component to L2 cache, only stores sharing information for blocks while L2 cache stores only data blocks exclusive with L1 cache. Shared L2 cache can increase total effective cache capacity on chip, but also increase the miss latency when data is on a remote node. Being different from Directory Cache structure, our proposal totally removes the directory from memory, which saves memory space and reduces access latency. Compared to L2 cache that combines directory information internally, our L2 cache structure saves up to 88% cache space and achieves similar performance.
|
|
| 5. |
- Faxén, Karl-Filip, et al.
(författare)
-
Multicore computing--the state of the art
- 2009
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- This document presents the current state of the art in multicore computing, in hardware and software, as well as ongoing activities, especially in Sweden. To a large extent, it draws on the presentations given at the Multicore Days 2008 organized by SICS, Swedish Multicore Initiative and Ericsson Software Research but the published literature and the experience of the authors has been equally important sources. It is clear that multicore processors will be with us for the foreseeable future; there seems to be no alternative way to provide substantial increases of microprocessor performance in the coming years. While processors with a few (2–8) cores are common today, this number is projected to grow as we enter the era of manycore computing. The road ahead for multicore and manycore hardware seems relatively clear, although some issues like the organization of the on-chip memory hierarchy remain to be settled. Multicore software is however much less mature, with fundamental questions of programming models, languages, tools and methodologies still outstanding.
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| 6. |
- Nikitovic, Mladen, et al.
(författare)
-
A study on periodic shutdown for adaptive CMPs in handheld devices
- 2008
-
Ingår i: 2008 13TH ASIA-PACIFIC COMPUTER SYSTEMS ARCHITECTURE CONFERENCE. - New York : IEEE. - 9781424426829 ; , s. 308-314
-
Konferensbidrag (refereegranskat)abstract
- The challenge to satisfy the demand for higher computing performance has become an increasingly difficult task to achieve. In the area of mobile devices, this demand has to be carefully balanced with an efficient use of the power source. We propose the use of an adaptive architecture that enables savings in power and energy in an intuitive way, considering the properties of future process technologies. We satisfy performance demand by utilizing thread-level parallelism and minimize the power and energy consumption by proposing an adaptive strategy that manages the power state of each individual CMP-core. In this study, we propose a periodical shutdown strategy and evaluate it in a multiprogrammed workload environment. Results show that a large amount of idle time, 77 %, can be saved by putting processors into power-saving states. Furthermore, introducing timeouts can dramatically decrease the number of state transitions.
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| 7. |
- Radu, M., et al.
(författare)
-
Work in progress - graduate exchange program in microelectronics system engineering
- 2008
-
Ingår i: FIE. - 9781424419692 ; , s. 563-564
-
Konferensbidrag (refereegranskat)abstract
- In todaypsilas world, where new technologies emerge and advance at a very fast pace every year, many professional societies are discussing moving to a Master level program as a ldquofirst professional degreerdquo, anticipating graduates with advances skills for tomorrowpsilas demanding and advanced industry. In this context, the education at the master level is becoming more and more important. Another key issue in todaypsilas world is the impact of globalization process (needs of multinational corporations). The engineering education must address the impact of global hiring. The graduates entering the global workplace must possess besides the essential technical skills, also cultural, social and communication skills, enabling them to work and interact in international environments, bringing creativity and innovative development in multi-cultural groups. In this context, exchange programs between different universities, located in different countries and continents are flourishing, the universities trying to integrate study-abroad components in their programs. This paper is presenting as a ldquoWork in Progressrdquo, the first steps related to an exchange program at the graduate level in the area of Microelectronics, between two prestigious universities located in USA (Rose Hulman Institute of Technology, Terre Haute, IN) and Sweden (Royal Institute of Technology, Stockholm). A Joint Degree or Dual Degree program at the Master Level is envisaged in the near future.
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