| 1. |
- Fretwell, P., et al.
(författare)
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Bedmap2 : improved ice bed, surface and thickness datasets for Antarctica
- 2013
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Ingår i: The Cryosphere. - : Copernicus GmbH. - 1994-0416 .- 1994-0424. ; 7:1, s. 375-393
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Tidskriftsartikel (refereegranskat)abstract
- We present Bedmap2, a new suite of gridded products describing surface elevation, ice-thickness and the seafloor and subglacial bed elevation of the Antarctic south of 60 degrees S. We derived these products using data from a variety of sources, including many substantial surveys completed since the original Bedmap compilation (Bedmap1) in 2001. In particular, the Bedmap2 ice thickness grid is made from 25 million measurements, over two orders of magnitude more than were used in Bedmap1. In most parts of Antarctica the subglacial landscape is visible in much greater detail than was previously available and the improved data-coverage has in many areas revealed the full scale of mountain ranges, valleys, basins and troughs, only fragments of which were previously indicated in local surveys. The derived statistics for Bedmap2 show that the volume of ice contained in the Antarctic ice sheet (27 million km(3)) and its potential contribution to sea-level rise (58 m) are similar to those of Bedmap1, but the mean thickness of the ice sheet is 4.6% greater, the mean depth of the bed beneath the grounded ice sheet is 72m lower and the area of ice sheet grounded on bed below sea level is increased by 10 %. The Bedmap2 compilation highlights several areas beneath the ice sheet where the bed elevation is substantially lower than the deepest bed indicated by Bedmap1. These products, along with grids of data coverage and uncertainty, provide new opportunities for detailed modelling of the past and future evolution of the Antarctic ice sheets.
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| 2. |
- Palesi, Maurizio, et al.
(författare)
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A Novel Mechanism to Guarantee In-Order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip
- 2010
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Ingår i: 13th Euromicro Conference On Digital System Design Architectures, Methods and Tools.
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Konferensbidrag (refereegranskat)abstract
- Although adaptive routing algorithms promise higher communication performance, as compared to deterministic routing algorithms, they suffer from the out-of-order packet delivery problem. In the context of Network on Chip, the area and computational overhead of ordering packets at the destination is high and may reverse any gain achieved through the use of adaptivity of the routing algorithm. In this paper, we describe a novel scheme for ensuring in-order packet delivery while retaining the performance advantages of adaptive routing. The hardware architecture of a router that supports the proposed scheme is described. Although the basic idea in our proposal is topology independent we evaluate and compare the performance of our scheme with both deterministic as well as adaptive routing algorithms for 2D mesh NoC. As compared to the XY routing algorithm, our technique significantly reduces the packet delay and improves the saturation point. The impact on router area and power dissipation is also discussed. Although the power consumption of routers increase, the energy consumption per flit increases less than 2% on average, since the higher performance allows for draining more traffic during a certain time window.
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| 3. |
- Palesi, Maurizio, et al.
(författare)
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Leveraging Partially Faulty Links Usage for Enhancing Yield and Performance in Network-on-Chip
- 2010
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Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - : IEEE Publisher. - 0278-0070 .- 1937-4151. ; Vol. 29:3, s. 426-440
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Tidskriftsartikel (refereegranskat)abstract
- The communication infrastructure of a complex multicore system-on-a-chip is getting an increasing fraction of the overall chip area. According to the International Technology Roadmap for Semiconductors, killer defect density does not decrease over successive technology generations. For this reason, the probability that a manufacturing defect affects the communication system is predicted to increase. In this paper, we deal with manufacturing defects which affect the links in a network on-chip-based interconnection system. The goal of this paper is to show that by using effective routing functions, supported by appropriate selection policies and with a limited amount of extra logic in the router, it is easy to exploit partially faulty links to improve the performance of the system. We show that, instead of discarding partially faulty links, they can be used at reduced capacity to improve the distribution of the traffic over the network, yielding performance and power improvements. We couple an application-specific routing function with a set of selection policies which are aware of link fault distribution and evaluate them on both synthetic traffic and a real complex multimedia application. We also present an implementation of the router, augmented with the extra logic, to support both the proposed selection functions and the transmission of messages over partially faulty links. We analyze the router in terms of silicon area, timing, and power dissipation.
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