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- Latif, Khalid, et al.
(author)
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A low-cost processing element recovery mechanism for fault tolerant Networks-on-Chip
- 2011
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In: Proc. NORCHIP. - United States : IEEE. - 9781457705144
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Conference paper (peer-reviewed)abstract
- A fault in one component of Networks-on-Chip (NoC) based system makes the fault-free connected units out of use and this in turn leads to considerable performance degradation. Many fault tolerant architectures and routing algorithms have already been proposed for NoC but the utilization of resources, affected indirectly by faults is yet to be addressed. It is indispensable step needed to be taken in order to implement the reliable on-chip systems especially with nano-scale technologies. In this paper, we present a technique to recover healthy processing elements for NoC architectures in case of associated routers failure by using the Partial Virtual-Channel Sharing (PVS) approach. The proposed architecture divides the network into cluster regions, where each cluster comprises of two nodes. Each node in a cluster provides a backup data-path for other node in the cluster. Each processing element can use the backup data-path to transmit and receive the packets in case of corresponding router failure. The simulation results show that the proposed architecture has low hardware overheads.
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| 4. |
- Rahmani, Amir-Mohammad, et al.
(author)
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A Stacked Mesh 3D NoC Architecture Enabling Congestion-Aware and Reliable Inter-layer Communication
- 2011
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In: 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing, PDP 2011. ; , s. 423-430
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Conference paper (peer-reviewed)abstract
- In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. Stacked mesh is a feasible architecture which takes advantage of the short inter-layer wiring delays, while suffering from inefficient intermediate buffers. To cope with this, an inter-layer communication mechanism is developed to enhance the buffer utilization, load balancing, and system fault-tolerance. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm for vertical communication. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10, and Negative Exponential Distribution (NED) traffic patterns. In addition, a video conference encoder has been used as a real application for system analysis. Our extensive experiments show significant power and performance improvements compared to a typical stacked mesh 3D NoC.
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| 5. |
- Rahmani, Amir-Mohammad, et al.
(author)
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Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures
- 2011
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In: 5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011. - New York, NY, USA : ACM. ; , s. 65-72
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Conference paper (peer-reviewed)abstract
- Three-dimensional IC technology offers greater device integration and shorter interlayer interconnects. In order to take advantage of these attributes, 3D stacked mesh architecture was proposed which is a hybrid between packet-switched network and a bus. Stacked mesh is a feasible architecture which provides both performance and area benefits, while suffering from inefficient intermediate buffers. In this paper, an efficient architecture to optimize system performance, power consumption, and reliability of stacked mesh 3D NoC is proposed. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called AdaptiveZ for vertical communication. In addition, we hybridize the proposed adaptive routing with available algorithms to mitigate the thermal issues by herding most of the switching activities closer to the heat sink. Our extensive simulations with synthetic and real benchmarks, including the one with an integrated videoconference application, demonstrate significant power, performance, and peak temperature improvements compared to a typical stacked mesh 3D NoC.
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| 6. |
- Rahmani, Amir-Mohammad, et al.
(author)
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Power-Efficient Inter-Layer Communication Architectures for 3D NoC
- 2011
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In: 2011 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011. - 9780769544472 ; , s. 355-356
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Conference paper (peer-reviewed)abstract
- In this work, an efficient hybridization architecture to optimize power consumption and system performance of Hybrid NoC-Bus 3D mesh is proposed. Hybrid NoC-Bus 3D mesh is a feasible architecture which takes advantage of the short interlayer wiring delays, while suffering from inefficient intermediate buffers. To address this issue, we propose a mechanism benefiting from a low-power congestion-aware routing algorithm for vertical communication. Our extensive simulations demonstrate significant power and performance improvements compared to a typical Hybrid NoC-Bus 3D architecture.
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