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Träfflista för sökning "WFRF:(Lemme Max C. 1970 ) srt2:(2004)"

Sökning: WFRF:(Lemme Max C. 1970 ) > (2004)

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1.
  • Lemme, Max C., 1970-, et al. (författare)
  • Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs
  • 2004
  • Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-74:SI, s. 346-350
  • Tidskriftsartikel (refereegranskat)abstract
    • New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.
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2.
  • Lemme, Max C., 1970-, et al. (författare)
  • Triple-gate metal-oxide-semiconductor field effect transistors fabricated with interference lithography
  • 2004
  • Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 15:4, s. S208-S210
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work, n-type triple-crate metal-oxide-semiconductor field effect transistors (MOSFETs) are presented, where laser interference lithography (LIL) is integrated into a silicon-on-insulator (SOI) CMOS process to provide for the critical definition of the transistor channels. A mix and match process of optical contact lithography and LIL is developed to achieve device relevant structures. The triple-gate MOSFETs are electrically characterized to demonstrate the feasibility of this low cost fabrication process.
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3.
  • Baus, M, et al. (författare)
  • Fabrication of monolithic bidirectional switch devices
  • 2004
  • Ingår i: Microelectronic Engineering. - 0167-9317 .- 1873-5568. ; 73-4, s. 463-467
  • Tidskriftsartikel (refereegranskat)abstract
    • The fabrication scheme of a novel MOS-based power device, a monolithic bidirectional switch (MBS), is presented. This concept allows the integration of a bidirectional switch with the advantages of low power consumption, small package size, and low fabrication costs. Furthermore, device simulations predict a performance benefit for power applications such as matrix converters. In an MBS, the field effect is used to control carrier concentrations in elevated structures made up of nearly intrinsic silicon. A CMOS-compatible nano-fabrication process for the MBS is proposed, employing local oxidation of silicon for self-aligned contact formation. First electrical results are presented. (C) 2004 Elsevier B.V. All rights reserved.
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4.
  • Efavi, J K, et al. (författare)
  • Investigation of NiAlN as gate-material for submicron CMOS technology
  • 2004
  • Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 76:1-4, s. 354-359
  • Tidskriftsartikel (refereegranskat)abstract
    • Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.
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5.
  • Henschel, W, et al. (författare)
  • Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates
  • 2004
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:5, s. 739-745
  • Tidskriftsartikel (refereegranskat)abstract
    • A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 run have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated.
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6.
  • Lemme, Max C., 1970-, et al. (författare)
  • Subthreshold behavior of triple-gate MOSFETs on SOI material
  • 2004
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 48:4, s. 529-534
  • Tidskriftsartikel (refereegranskat)abstract
    • The fabrication of n-type multi-wire MOSFETs on SOI material with triple-gate structures is presented. The output and transfer characteristics of devices with a gate length of 70 nm and a MESA width of 22 nm demonstrate clearly the suppression of short channel effects (SCE). In addition, these triple-gate structures are compared with planar SOI devices of comparable dimensions. The influence of biasing the substrate (back gate) is analyzed and compared to simulation data.
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  • Resultat 1-6 av 6

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