| 1. |
- Bell, D. C., et al.
(författare)
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Precision cutting and patterning of graphene with helium ions
- 2009
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 20:45, s. 455301-
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Tidskriftsartikel (refereegranskat)abstract
- We report nanoscale patterning of graphene using a helium ion microscope configured for lithography. Helium ion lithography is a direct-write lithography process, comparable to conventional focused ion beam patterning, with no resist or other material contacting the sample surface. In the present application, graphene samples on Si/SiO(2) substrates are cut using helium ions, with computer controlled alignment, patterning, and exposure. Once suitable beam doses are determined, sharp edge profiles and clean etching are obtained, with little evident damage or doping to the sample. This technique provides fast lithography compatible with graphene, with similar to 15 nm feature sizes.
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| 2. |
- Gottlob, H. D. B., et al.
(författare)
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Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics
- 2009
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 86:7-9, s. 1642-1645
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Tidskriftsartikel (refereegranskat)abstract
- We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd2O3) from a silicon oxide (SiO2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs). (C) 2009 Elsevier B.V. All rights reserved.
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| 3. |
- Bell, David C., et al.
(författare)
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Precision material modification and patterning with He ions
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:6, s. 2755-2758
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the use of a helium ion microscope as a potential technique for precise nanopatterning. Combined with an automated pattern generation system, they demonstrate controlled etching and patterning of materials, giving precise command over the geometery of the modified nanostructure. After the determination of suitable doses, sharp edge profiles and clean etching of areas in materials were observed. In this article they present examples of patterning on SiO(2) and graphene, which is particularly relevant. This technique could be an avenue for precise material modification for future graphene based device fabrication. The technique has the potential to revolutionize the way that very thin, one-atomic layer materials are modified in a controlled and predictable way.
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| 4. |
- Benetti, M., et al.
(författare)
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POLYSILICON MESOSCOPIC WIRES COATED BY Pd AS H(2) SENSORS
- 2009
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Ingår i: PROCEEDINGS OF THE 13TH ITALIAN CONFERENCE ON SENSORS AND MICROSYSTEMS. - SINGAPORE : WORLD SCIENTIFIC PUBL CO PTE LTD. ; , s. 161-165
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Konferensbidrag (refereegranskat)abstract
- In this work a novel monocrystalline silicon nanowires array has been investigated and presented as hydrogen sensor, designed and fabricated by employing high resolution microfabrication techniques and featuring a high surface/volume ratio. The nanowires arrays makes up the channel of a MOS system, palladium-silicon dioxide-silicon. Several devices have been fabricated by using a SOI (Silicon On Insulator) substrate, Source and Drain have been geometrically patterned by optical lithography and Boron p-doped. Electron Beam Litography (EBL) defined the MOS channel made up of a nanowires array of different length and width in different transistors. The pads of Source and Drain have been manufactured with an aluminium film deposition. The Gate has been fabricated with a grown silicon oxide layer (17.4 nm) and Palladium has been used as gate contact. Polarizing and exposing the device to H(2)/N(2) cycles at different concentrations some preliminary measurements have been successfully conducted.
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| 5. |
- Lemme, Max C., 1970-, et al.
(författare)
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Etching of Graphene Devices with a Helium Ion Beam
- 2009
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Ingår i: ACS Nano. - : American Chemical Society (ACS). - 1936-0851 .- 1936-086X. ; 3:9, s. 2674-2676
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Tidskriftsartikel (refereegranskat)abstract
- We report on the etching of graphene devices with a helium ion beam, including in situ electrical measurement during lithography. The etching process can be used to nanostructure and electrically isolate different regions In a graphene device, as demonstrated by etching a channel in a suspended graphene device with etched gaps down to about 10 nm. Graphene devices on silicon dioxide (02) substrates etch with lower He ion doses and are found to have a residual conductivity after etching, which we attribute to contamination by hydrocarbons.
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| 6. |
- Geringer, V., et al.
(författare)
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Intrinsic and extrinsic corrugation of monolayer graphene deposited on SiO(2)
- 2009
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Ingår i: Physical Review Letters. - 0031-9007 .- 1079-7114. ; 102:7, s. 076102-
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Tidskriftsartikel (refereegranskat)abstract
- Using scanning tunneling microscopy in an ultrahigh vacuum and atomic force microscopy, we investigate the corrugation of graphene flakes deposited by exfoliation on a Si/SiO(2) (300 nm) surface. While the corrugation on SiO(2) is long range with a correlation length of about 25 nm, some of the graphene monolayers exhibit an additional corrugation with a preferential wavelength of about 15 nm. A detailed analysis shows that the long-range corrugation of the substrate is also visible on graphene, but with a reduced amplitude, leading to the conclusion that the graphene is partly freely suspended between hills of the substrate. Thus, the intrinsic rippling observed previously on artificially suspended graphene can exist as well, if graphene is deposited on SiO(2).
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| 7. |
- Gottlob, H. D. B., et al.
(författare)
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Gd silicate : A high-k dielectric compatible with high temperature annealing
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 249-252
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Tidskriftsartikel (refereegranskat)abstract
- The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd(2)O(3)) and silicon oxide (SiO(2)) on silicon substrates are compared after annealing at temperatures up to 1000 degrees C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO(2) layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.
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| 8. |
- Lemme, Max C., 1970-, et al.
(författare)
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Complementary metal oxide semiconductor integration of epitaxial Gd(2)O(3)
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567. ; 27:1, s. 258-261
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, epitaxial gadolinium oxide (Gd(2)O(3)) is reviewed as a potential high-K gate dielectric, both "as deposited" by molecular beam epitaxy as well as after integration into complementary metal oxide semiconductor (CMOS) processes. The material shows promising intrinsic properties, meeting critical ITRS targets for leakage current densities even at subnanometer equivalent oxide thicknesses. These epitaxial oxides can be integrated into a CMOS platform by a "gentle" replacement gate process. While high temperature processing potentially degrades the material, a route toward thermally stable epitaxial Gd(2)O(3) gate dielectrics is explored by carefully controlling the annealing conditions.
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| 9. |
- Lemme, Max C., 1970-
(författare)
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Current Status of Graphene Transistors
- 2009
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Ingår i: Solid State Phenomena. - 1012-0394 .- 1662-9779. ; 156, s. 499-509
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Tidskriftsartikel (refereegranskat)abstract
- This paper reviews the current status of graphene transistors as potential supplement to silicon CMOS technology. A short overview of graphene manufacturing and metrology methods is followed by an introduction of macroscopic graphene field effect transistors (FETs). The absence of an energy band gap is shown to result in severe shortcomings for logic applications. Possibilities to engineer a band gap in graphene FETs including quantum confinement in graphene Nanoribbons (GNRs) and electrically or substrate induced asymmetry in double and multi layer graphene are discussed. Novel switching mechanisms in graphene transistors are briefly introduced that could lead to future memory devices. Finally, graphene FETs are shown to be of interest for analog radio frequency applications.
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| 10. |
- Lu, Y., et al.
(författare)
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Leakage current effects on C-V plots of high-k metal-oxide-semiconductor capacitors
- 2009
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Ingår i: Journal of Vacuum Science & Technology B. - : American Vacuum Society. - 1071-1023 .- 1520-8567 .- 2166-2754 .- 2166-2746. ; 27:1, s. 352-355
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Tidskriftsartikel (refereegranskat)abstract
- With the employment of ultrathin, high dielectric constant gate materials in advanced semiconductor technology, the conventional capacitance-voltage measurement technique exhibits a series of anomalies. In particular, a nonsaturating increase in the accumulation capacitance with reducing measurement frequency is frequently observed, which has not been adequately explained to our knowledge. In this article, the authors provide an explanation for this anomaly and hence set a criterion for the lower bound on measurement frequency. We then present a model which allows the easy extraction of the required parameters and apply it to an experimental set of data.
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| 11. |
- Peibst, R., et al.
(författare)
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PECVD grown Ge nanocrystals embedded in SiO(2) : From disordered to templated self-organization
- 2009
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Ingår i: MICROELECTRONICS JOURNAL. - : Elsevier BV. - 0026-2692. ; 40:4-5, s. 759-761
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Tidskriftsartikel (refereegranskat)abstract
- We present a new "templated self-organization" method for the preparation of Ge nanocrystals in SiO(2) that combines a bottom-up with a top-down approach for nanostructuring. Ge nanocrystals are formed by self-organization induced by thermal annealing of thin Ge films embedded ill SiO(2) whose areas are predefined by nanoimprint patterning. Thus Much smaller Structure sizes call be achieved than by pure nanostructuring and touch more regular structures call be prepared than by pure self-organization. in particular, the method enables the generation of Ge nanocrystals of equal size at predefined vertical and lateral positions thus facilitating the fabrication of nanoscaled devices due to the Suppression of Structural fluctuations.
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| 12. |
- Schmidt, M., et al.
(författare)
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Mobility extraction in SOI MOSFETs with sub 1 nm body thickness
- 2009
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Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101 .- 1879-2405. ; 53:12, s. 1246-1251
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Tidskriftsartikel (refereegranskat)abstract
- In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem, Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in Such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.
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| 13. |
- Schmidt, M., et al.
(författare)
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Mobility Extraction of UTB n-MOSFETs down to 0.9 nm SOI thickness
- 2009
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Ingår i: ULIS 2009. - NEW YORK : IEEE. ; , s. 27-30
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Konferensbidrag (refereegranskat)abstract
- In this abstract, the impact of series resistance on mobility extraction in conventional and recessed-gate ultra thin body (UTB) n-MOSFETs is investigated. High series resistance leads to an overestimation of the internal source / drain voltage and influences the measurement of the gate to channel capacitance. A specific MOSFET design that includes additional channel contacts and recessed gate technology are used to successfully extract mobility down to 0.9 nm silicon film thickness (4 atomic layers). Quantum mechanical effects are found to shift the threshold voltage and degrade mobility at these extreme scaling limits.
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