SwePub - sökning: WFRF:(O'Nils Mattias)

Numrering	Referens	Omslagsbild	Hitta
1.	Abdalla, Suliman, et al. (författare) Architecture and Circuit Design for Color X-Ray Pixal Array Detector Read-Out Electronics 2007 Ingår i: 24th Norchip Conference, 2006. - New York : IEEE conference proceedings. - 9781424407729 ; , s. 271-276 Konferensbidrag (refereegranskat)abstract This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.
2.	Alfredsson, Jon (författare) Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies 2008 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)
3.	Cao, Cao, et al. (författare) Synthesis tool for low-power finite-state machines with mixed synchronous/asynchronous state memory 2006 Ingår i: IEE Proceedings - Computers and digital Techniques. - : Institution of Engineering and Technology (IET). - 1350-2387 .- 1359-7027. ; 153:4, s. 243-248 Tidskriftsartikel (refereegranskat)abstract An efficient way to obtain finite-state machines (FSMs) with low-power consumption is to partition the machine into two or more sub-FSMs and then use dynamic power management where all sub-FSMs not active are shut down, with the effect of reducing dynamic power dissipation. Thus, FSM partitioning algorithms and register-transfer-level power estimation functions are the main focus of the paper as these are key issues in the design of a computer-aided design tool for synthesis of low-power partitioned FSMs. An implementation architecture is targeted, which is based on both synchronous and asynchronous state memory elements that enable larger power reductions than fully synchronous architectures do. Power reductions of up to 77 have been achieved at a cost of an 18 increase in area.
4.	Lawal, Najeem, et al. (författare) Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems 2005 Ingår i: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL. - : IEEE conference proceedings. - 0780393627 ; , s. 136-141 Konferensbidrag (refereegranskat)abstract FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.
5.	Lawal, Najeem, et al. (författare) C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation 2006 Ingår i: Proceedings of the FPGA World Conference 2006. Konferensbidrag (refereegranskat)abstract Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have shown to be an effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain data flow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.
6.	Lawal, Najeem, et al. (författare) Embedded FPGA memory requirements for real-time video processing applications 2005 Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 206-209 Konferensbidrag (refereegranskat)abstract FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures
7.	Lawal, Najeem, 1974- (författare) Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems 2009 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance. Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
8.	Lawal, Najeem, 1974- (författare) Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems 2006 Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance. Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis. A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components. The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.
9.	Lawal, Najeem, et al. (författare) Power-aware automatic constraint generation for FPGA based real-time video processing systems 2007 Ingår i: 25th Norchip Conference, NORCHIP. - New York : IEEE conference proceedings. - 9781424415168 ; , s. 124-128 Konferensbidrag (refereegranskat)abstract The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.
10.	Lawal, Najeem, et al. (författare) Ram allocation algorithm for video processing applications on FPGA 2006 Ingår i: Journal of Circuits, Systems and Computers. - 0218-1266. ; 15:5, s. 679-699 Tidskriftsartikel (refereegranskat)abstract This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.
11.	Lepistö, Niklas, et al. (författare) Design and Implementation of Video Pre-Processor for FPGA based SoC 2008 Konferensbidrag (refereegranskat)abstract FPGA based implementation of embedded systems has many attractive characteristics such as: flexibility, low cost, high integration, embedded distributed memories and ex-tensive parallelism. Real-time video processing is an ap-plication area where FPGA based implementations have significant potential. This paper presents the design and implementation of a video pre-processor suitable for use in embedded display applications. Some of the key functions of the pre-processor are cropping and scaling of input video frames and the possibility to use multiple pre-processors in parallel to provide multiple video streams to a display unit
12.	Lepistö, Niklas, et al. (författare) Design Exploration of Video Pre-Processor for FPGA based SoC 2006 Ingår i: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). - Berlin : Springer Verlag. - 354036708X - 9783540367086 ; , s. 87-92 Konferensbidrag (refereegranskat)abstract FPGA based implementation of embedded systems has many attractive characteristics such as: flexibility, low cost, high integration, embedded distributed memories and extensive parallelism. One application where there is a significant possible potential for FPGA is for the implementation of real-time video processing. In this paper we present an analysis of a video pre-processor and how this affects the FPGA and RAM resource usage and performance. From these results we indicate the best space-time mapping of operations under different design constraints. These results can be used as a decision base when implementing an FPGA based video enabled display unit.
13.	Lepistö, Niklas (författare) FPGA based architectures for embedded video systems 2008 Licentiatavhandling (övrigt vetenskapligt/konstnärligt)
14.	Lepistö, Niklas, et al. (författare) High Performance FPGA based Camera Architecture for Range Imaging 2005 Ingår i: 23rd NORCHIP Conference 2005. - : IEEE conference proceedings. - 1424400643 ; , s. 165-168 Konferensbidrag (refereegranskat)abstract Range imaging is often used in classification of objects in process industry. The speed of inspection needs to be high, so it does not become the bottleneck in the process. This paper presents an FPGA based architecture for range imaging. Using centre of gravity it calculates the range positions from 2D images. The results show that the proposed architecture can process range values with a performance up to 150 Msamples per second. Thus, using cheep standard technology we can achieve up to 3 times higher performance than expensive state-of-the-art high performance smart-cameras.
15.	Lundgren, Jan, et al. (författare) An Area Efficient Readout Architecture for Photon Counting Color Imaging 2007 Ingår i: Nuclear Instruments and Methods in Physics Research Section A. - : Elsevier BV. - 0168-9002 .- 1872-9576. ; 576:1, s. 132-136 Tidskriftsartikel (refereegranskat)abstract The introduction of several energy levels, namely color imaging, in photon counting X-ray image sensors is a trade-off between circuit complexity and spatial resolution. In this paper we propose a pixel architecture that has full resolution for the intensity and uses sub-sampling for the energy spectrum. The results show that this sub-sampling pixel architecture produces images with an image quality which is, on average, 2.4 dB (PSNR) higher than those for a single energy range architecture and with half the circuit complexity of that for a full sampling architecture.
16.	Lundgren, Jan, 1977- (författare) Behavioral Level Simulation Methods for Early Noise Coupling Quantification in Mixed-Signal Systems 2005 Licentiatavhandling (övrigt vetenskapligt/konstnärligt)abstract In this thesis, noise coupling simulation is introduced into the behavioral level. Methods and models for simulating on-chip noise coupling at a behavioral level in a design flow are presented and verified for accuracy and validity. Today, designs of electronic systems are becoming denser and more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. This raises problems when the electronics components start to interfere with each other. Often, digital components disturb analog components, introducing noise into the system causing degradation of the performance or even introducing errors into the functionality of the system. Today, these effects can only be simulated at a very late stage in the design process, causing large design iterations and increased costs if the designers are required to return and make alterations, which may have occurred at a very early stage in the process. This is why the focus of this work is centered on extracting noise coupling simulation models that can be used at a very early design stage such as the behavioral level and then follow the design through the various design stages. To realize this, SystemC is selected as a platform and implementation example for the behavioral level models. SystemC supports design refinement, which means that when designs are being refined and are crossing the design levels, the noise coupling models can also be refined to suit the current design. This new way of thinking in primarily mixed-signal designs is called Behavioral level Noise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costs of design iterations due to component cross-talk and simplifies the work for mixed-signal system designers.
17.	Lundgren, Jan, et al. (författare) Evaluation of Mixed-Signal Noise Effects in Photon Counting X-Ray Image Sensor Readout Circuits 2006 Ingår i: Nuclear Instruments and Methods in Physics Research Section A. - : Elsevier BV. - 0168-9002 .- 1872-9576. ; 563:1, s. 88-91 Tidskriftsartikel (refereegranskat)abstract In readout electronics for photon counting pixel detectors, the tight integration between analog and digital blocks causes the readout electronics to be sensitive to on-chip noise coupling. This noise coupling can result in faulty luminance values in grayscale X-ray images, or as color distortions in a color X-ray imaging system. An exploration of simulating noise coupling in readout circuits is presented which enables the discovery of sensitive blocks at as early a stage as possible, in order to avoid costly design iterations. The photon counting readout system has been simulated for noise coupling in order to highlight the existing problems of noise coupling in X-ray imaging systems. The simulation results suggest that on-chip noise coupling should be considered and simulated in future readout electronics systems for X-ray detectors.
18.	Lundgren, Jan, et al. (författare) Power Distribution and Substrate Noise Coupling Investigations on the Behavioral Level for Photon Counting Imaging Readout Circuits 2007 Ingår i: Nuclear Instruments and Methods in Physics Research Section A. - : Elsevier BV. - 0168-9002 .- 1872-9576. ; 576:1, s. 113-117 Tidskriftsartikel (refereegranskat)abstract In modern mixed-signal system design, there are increasing problems associated with noise coupling caused by switching digital parts to sensitive analog parts. As a consequence, there is a growing necessity to understand these problems. In order to avoid costly design iterations, noise coupling simulations should be initiated as early as possible in the design chain. The problems associated with on-chip noise coupling have been discovered in photon counting pixel detector readout systems, where the level of integration of analog and digital circuits is very high on a very small area, and it would appear that these problems will continue to increase for future system designs in this field. This paper deals with the functionality of utilizing behavioral level models for simulating noise coupling in these readout systems. The methods and models are described and simulation results are shown for a photon counting pixel detector readout system.
19.	Lundgren, Jan, et al. (författare) Simplified Gate Level Noise Injection Models for Behavioral Noise Coupling Simulation 2005 Ingår i: Proceedings of the 2005 European Conference on Circuit Theory and Design. - Piscataway, NJ, USA : IEEE conference proceedings. - 0780390660 - 9780780390669 ; , s. 345-348 Konferensbidrag (refereegranskat)abstract In CMOS digital logic, there are two major noise sources requiring consideration. These are a circuit´s power supply current and its noise current injected into the substrate of the circuit. This paper proposes a method for modeling and estimating the noise current injected into the substrate by capacitive coupling in digital circuits. The simplicity of the model and the reduction of details in the technology libraries facilitates behavioral level noise coupling simulation. The model is exemplified and evaluated for a simple NOT gate test case, for which the accuracy and simplicity of the models show great promise for simulation at the behavioral level.
20.	Lundgren, Jan, 1977- (författare) Simulating Behavioral Level On-Chip Noise Coupling 2007 Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract In this thesis, noise coupling simulation is introduced into the behavioral level. Methods andmodels for simulating on-chip noise coupling at the behavioral level in a design flow are presentedand verified for accuracy and validity. Today, designs of electronic systems are becoming denserand more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. Thisraises problems when the electronics components start to interfere with each other. Often, digitalcomponents disturb analog components, introducing noise into the system causing degradation ofthe performance or even introducing errors into the functionality of the system.Today, these effects can only be simulated at a very late stage in the design process, causinglarge design iterations and increased costs if the designers are required to return and makealterations, which may have occurred at a very early stage in the process.This is why the focus of this work is centered on extracting noise coupling simulation modelsthat can be used at a very early design stage, such as at the behavioral level and then follow thedesign through the various design stages. To achieve this, SystemC is selected as a platform andimplementation example for the behavioral level models. SystemC supports design refinement,which means that when designs are being refined and are crossing the design levels, the noisecoupling models can also be refined to suit the current design.This new method of thinking in primarily mixed-signal designs is called Behavioral levelNoise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costsof design iterations due to component cross-talk and simplifies the work for mixed-signal systemdesigners.
21.	Nordin, Lisa, 1981-, et al. (författare) Characterization and classification of dewatering measurement techniques for mechanical pulps 2008 Ingår i: Proceedings of the PRS, Finland, May 2008.. Konferensbidrag (refereegranskat)
22.	Nordin, Lisa, 1981-, et al. (författare) Measurement and prediction of dewatering characteristics for mechanical pulps using optical fibre analyzers 2009 Ingår i: Proceedings - 2009 International Mechanical Pulping Conference, IMPC 2009. ; , s. 309-316 Konferensbidrag (refereegranskat)abstract The aim of this work was to obtain an on-line measurement for dewatering behaviour in the wire section based on fibre and fines characteristics. Four laboratory dewatering equipments were compared and the fibre characteristics were measured by means of optical fibre analyzers. The results show that rough correlations do appear to exist between the dewatering equipments; however they rank the pulps differently depending on the raw wood material used and whether the refining conditions are mild or harsh. The prediction models based on fibre characteristics showed a high degree of statistical accuracy. The descriptions, however, proved not to be sufficiently good with regards to the dewatering behaviour for them to be used in relation to on-line applications. This might have been because consideration was not given to some important variables which do, in fact, have a significant impact on the drainability. These variables could include physical fibre properties or others that are not measured, or properties that, at present, are unable to be measured at a sufficient resolution.
23.	Norell, Håkan, et al. (författare) A Generalized Architecture for Hardware Synthesis of Spatio-Temporal Memory Models for Image Processing Systems 2005 Ingår i: IWSSIP 2005 - Proceedings of the 12th International Worshop on Systems, Signals & Image Processing. - : InderScience Publishers. - 0907776205 ; , s. 361-365 Konferensbidrag (refereegranskat)abstract This paper presents a generalized architecture for the synthesis of application specific memory architectures for real-time image processing systems. The memory generation presented in this paper can handle both spatial and spatio-temporal memory models. The results show that the architecture efficiently solves the problems related to memory accesses for most of the available video image processing filters available at present.
24.	Norell, Håkan, et al. (författare) Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems 2007 Ingår i: EURASIP Journal on Embedded Systems. - : Springer Science and Business Media LLC. - 1687-3955 .- 1687-3963. ; 2007 Tidskriftsartikel (refereegranskat)abstract This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.
25.	Norell, Håkan, et al. (författare) VIPS: Video Image Processing In a Second 2006 Konferensbidrag (refereegranskat)
26.	Norlin, Börje, 1967-, et al. (författare) Energy Resolved X-ray Imaging as a Tool for Characterization of Paper Coating Quality 2009 Ingår i: IEEE Nuclear Science Symposium Conference Record 2009. - : IEEE conference proceedings. - 9781424439621 ; , s. 1703-1706 Konferensbidrag (refereegranskat)abstract Energy resolved X-ray imaging can be used as a tool to analyze the variation in the chemical content of an object. In this work we have used energy resolved X-ray imaging to measure the variation in the chemical content of paper and paper coating. This is an important quality parameter for the paper industry. In order to separate the variation in coating thickness from the variation in paper thickness, energy resolution is used to separate the response of the coating from the response of the paper. The MEDIPIX2 single photon processing X-ray imaging system [1] has been used in the measurements. The measurement results are compared to simulations with MCNP. The influence of charge sharing is discussed and the effects have been studied by comparing results from detectors with 220x220 µm2 pixels and detectors with 55x55 µm2 pixels. There is a trade-off between good spatial resolution obtained with detectors with small pixels and good energy resolution obtained with detectors with large pixels. The requirements on image quality, to achieve the resolution of coating distribution relevant for the application, are discussed.
27.	O'Nils, Mattias, et al. (författare) A Project Based Master's Programme for SoF/SoC based Sensor Systems 2005 Ingår i: Proceedings of the 2005 European Conference on Circuit Theory and Design. - : IEEE conference proceedings. - 0780390660 ; , s. 123-126 Konferensbidrag (refereegranskat)abstract We forsee an increase in communicating sensor systems, that we call Sensible Things that Communicate (STC). These systems range from simple powerless systems for control or classification. In this paper we present the curriculum and pedagogical methods used in a Master's programme developed to meet the requirements that STC systems put on a designer. The goal for the program has been to encurage the students to acquire knowlege from completing practical design cases, of industrial or academic interest. This has shown to be an effective method to learn an motivate the students.
28.	O'Nils, Mattias, et al. (författare) Data Partitioning for Parallel Implementation of Real-Time Video Processing Systems 2005 Ingår i: Proceedings of the 2005 European Conference on Circuit Theory and Design. - : IEEE conference proceedings. - 0780390660 - 9780780390669 ; , s. 213-216 Konferensbidrag (refereegranskat)abstract The main reason for using data partitioning for a video processing system is the increase in performance it offers. This paper presents a comparison of the buffering requirements for different data partitioning methods used in video processing systems. The analysis shows that the buffer storage required for the implementation of video systems is highly dependent on the partitioning strategy. The results indicate that partitioning the tasks vertically is by far the most efficient method when considering buffer sizes.
29.	O'Nils, Mattias, 1969-, et al. (författare) High-Level SystemC Synthesis for FPGA based Real-Time Video Processing Systems 2006 Ingår i: Proceedings of the FPGA World Conference. Konferensbidrag (refereegranskat)
30.	O'Nils, Mattias, 1969-, et al. (författare) Threshold Modulation for Continuous Energy Resolution with Two Channels per Pixel in a Photon Counting X-ray Image Detector 2009 Ingår i: Nuclear Instruments and Methods in Physics Research Section A. - : Elsevier. - 0168-9002 .- 1872-9576. ; 607:1, s. 236-239 Tidskriftsartikel (refereegranskat)abstract The introduction of energy resolution in X-ray image detectors will lead to tradeoffs between circuit complexity and spatial/energy resolution in the pixel design. The proposed method provides continuous energy resolution with only two energy channels per pixel, which is a comparable complexity to that of a window discriminator pixel like Medipix2. The paper illustrates the method and validates the method through analytical analysis and through simulation of real and synthetic data.
31.	Thim, Jan, et al. (författare) Realizing increased sub-pixel spatial resolution in X-ray imaging using displaced multiple images 2009 Ingår i: 11th International Workshop on Radiation Imaging Detectors. Konferensbidrag (refereegranskat)abstract In X-Ray imaging with pixel detector systems, the resolution of the image taken is dependant on the pixel size in the detector readout electronics. Depending on the functionality of the readout electronics, the surface space on the readout chip for each pixel has a minimum size, which sets the spatial resolution of the taken images. For applications where it is required to image extremely small structures in a material, the spatial resolution of the X-Ray detector system sets the limit, and readout systems with high functionality cannot be considered. One way to reach sub-pixel resolution is to use a nanofocus source to achieve an X-ray microscopy setup [1]. However, this type of X-ray source is still too expensive to be an alternative for quality assurance systems used in the industry. In this paper we focus on a much simpler way of increasing spatial resolution that has proven effective in images for visible light. By mounting either the objects for imaging or the image sensor system on a step motor table and take multiple images slightly dislocated from one another, an increase in sub-pixel spatial resolution can be achieved. Consider the case that an image sensor system with a pixel size of 55x55 µm is available for an imaging application that requires a resolution of 20x20 µm. The application is material characterization and allows for multiple images to be taken for one sample. In this case, increasing the sub-pixel resolution by nine times (3x3) will result in a pixel size of about 18x18 µm, which would meet the requirements. This can be realized by taking nine images dislocated 1/3 of the pixel width from each other. If the upper left pixel of the centre image has coordinates (0,0) the upper left pixel of all the nine images will have coordinates (-1/3,1/3), (0,1/3), (1/3,1/3), (-1/3,0), (0,0), (1/3,0), (-1/3,-1/3), (0,-1/3) and (1/3,-1/3). The result of a direct combination of these images is illustrated in Figure 1, where one of nine images is shown at the left. Combining the images without images processing with an algorithm will yield the image in the centre, which can be compared to how the image would look in full 9x resolution (right image). As can be seen, some details are lost and the image is blurred compared to a full resolution image. However, with an image processing algorithm in the combination phase this effect can be reduced and the image quality increased. This paper shows simulated and measured results from using dislocation imaging in X-Ray imaging systems, where the test case system will be the MEDIPIX2 system [2]. An investigation of different image processing algorithms suitable for this type of imaging is conducted. An investigation is also done to show whether detectors with large size pixels compared to the standard size in a MEDIPIX system can be combined with the described sub-pixel scaling technique. The result of this combination is used to investigate the charge sharing effects on the MEDIPIX system. [1] Norlin B., Fröjdh C., Nuclear Instruments and Methods, sect. A (2009), doi:10.1016/j.nima.2009.03.155[2] Llopart X., Campbell M., Dinapoli R., san Segundo D., Pernigotti E., IEEE Transactions on Nuclear Science, Vol. 49, Issue 5, Part 1, pp. 2279-2283, October 2002. Figure 1. Image (left) with 50x50 pixels, with the resulting combination of nine images forming an image with a sub-pixel resolution of 150x150 pixel (centre), compared to a full resolution reference image (right).
32.	Thim, Jan, 1977-, et al. (författare) Simulating the Impact of Topographical Microstructures on Triangulation Measurement Setups using Matlab 2008 Ingår i: Proceedings of Nordic MATLAB User Conference. Konferensbidrag (refereegranskat)abstract The paper manufacturing industry is currently exploring the possibility of measuring micro structural topography online in a paper manufacturing machine, which is intended to lead to a more precise measure of the paper quality reel to reel and a more efficient use of raw material. This paper presents a Matlab simulation model that can be used to configure such measurement readout systems, and includes a demonstration of the model in use. The model will also be used for research purposes in order to assist in gaining a better understanding of both the limitations and possibilities of such measurement systems. In this regard the angular shading of microstructures and Centre of Gravity (CoG) functions are included in the attributes that require further exploration.
33.	Thörnberg, Benny, et al. (författare) Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems 2007 Ingår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. - 0278-0070 .- 1937-4151. ; 26:4, s. 781-800 Tidskriftsartikel (refereegranskat)abstract The great variety of pixel dynamics of real-time video processing systems, ranging from color, grayscale or binary pixels, means that a careful design and specification of bit-widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an Integer Non Linear Program (INLP) formulation for the optimization of the memory hierarchy of real-time video processing systems. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61 percent compared to a non optimal memory hierarchy.
34.	Thörnberg, Benny, et al. (författare) Impact of Bit-Width specification on the memory hierarchy for a real-time video processing system 2006 Ingår i: Proceedings -Design, Automation and Test in Europe, DATE. - Piscataway, NJ : IEEE conference proceedings. - 9783981080117 ; , s. 750-751 Konferensbidrag (refereegranskat)abstract The great variety of pixel dynamics of real-time video processing systems, ranging from color, grayscale or binary pixels, means that a careful design and specification of bit-widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. A real-life surveillance system is introduced, as a demonstration application showing how the optimal allocation of shift registers for the storage of intermediate results is sensitive to bit-widths. From this we conclude, that careful memory hierarchy design where bit-widths are considered can reduce the total on-chip memory storage requirement by 61 percent compared to a non-optimal design.
35.	Thörnberg, Benny, et al. (författare) Optimization of memory allocation for real-time video processing on FPGA 2005 Ingår i: 16th International Workshop on Rapid System Prototyping, Proceedings - SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE. - : IEEE conference proceedings. - 0769523617 ; , s. 141-147 Konferensbidrag (refereegranskat)abstract We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.
36.	Thörnberg, Benny, et al. (författare) Polyhedral space generation and memory estimation from interface and memory models of real-time video systems 2006 Ingår i: Journal of Systems and Software. - : Elsevier BV. - 0164-1212 .- 1873-1228. ; 79:2, s. 231-245 Tidskriftsartikel (refereegranskat)abstract We present a tool and a methodology for estimating the memory storage requirement for synchronous real-time video processing systems. Typically, a designer will use the feedback information from this estimation to select the most optimal execution order for software processors or space to time mapping for hardware. We propose to start from a conceptual interface and memory model that captures memory usage and data transfers. This high-level modeling is provided as an extension library of SystemC called IMEM. A common polyhedral iteration space is generated from the model, where polytopes are placed using a new placement algorithm based on simple heuristics. This algorithm will ensure maximum freedom of selecting executing order as all negative dependencies are removed to the length of zero. A demonstration is given regarding how the polytopes and dependency vectors can then be used as input to a memory storage estimation tool called STOREQ.

Skapa referenser, mejla, bekava och länka

Länka till träfflistan

Träfflista för sökning "WFRF:(O'Nils Mattias) srt2:(2005-2009)"

Avgränsa träffmängd

År