| 1. |
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| 2. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
A composable and predictable MPSoC design flow for multiple real-time applications
- 2016
-
Ingår i: Model-Implementation Fidelity in Cyber Physical System Design. - Cham : Springer International Publishing. ; , s. 157-174
-
Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- Design of real-time MPSoC systems including multiple applications is challenging because temporal requirements of each application must be respected throughout the entire design flow. Currently the design of different applications is often interdependent, making converge to a solution for each application difficult. This chapter proposes a compositional method to design applications independently, and then to execute them without interference. We define a formal modeling framework as a suitable entry point for application design. The models are executable, which enables early detection of specification errors, and include the formal properties of the applications based on well-defined models of computation. We combine this with a predictable MPSoC platform template that has a supporting design flow but lacks a simulation front-end. The structure and behavior of the application models are exported to an intermediate format via introspection which is iteratively transformed for the backend flow. We identify the problems arising in this transformation and provide appropriate solutions. The design flow is demonstrated by a system consisting of two streaming applications where less than half of the design time is dedicated to operating on the integrated system model.
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| 3. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
A Composable and Predictable MPSoC Design Flow for Multiple Real-Time Applications
- 2015
-
Konferensbidrag (refereegranskat)abstract
- Design of real-time MPSoC systems including multiple appli-cations is challenging because temporal requirements of each applicationmust be respected throughout the entire design flow. Currently the de-sign of different applications is often interdependent, making converge toa solution for each application difficult. This paper proposes a composi-tional method to design applications independently, and then to executethem without interference. We define a formal modeling framework as asuitable entry point for application design. The models are executable,which enables early detection of specification errors, and include the for-mal properties of the applications based on well-defined models of com-putation. We combine this with a predictable MPSoC platform templatethat has a supporting design flow but lacks a simulation front-end. Thestructure and behavior of the application models are exported to an in-termediate format via introspection which is iteratively adapted for thebackend flow. We identify the problems arising in this adaptation andprovide appropriate solutions. The design flow is demonstrated by a sys-tem consisting of two streaming applications where less than half of thedesign time is dedicated to operating on the integrated system model.
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| 4. |
- Attarzadeh-Niaki, Seyed-Hosein, 1984-, et al.
(författare)
-
An extensible modeling methodology for embedded and cyber-physical system design
- 2016
-
Ingår i: Simulation (San Diego, Calif.). - : Sage Publications. - 0037-5497 .- 1741-3133. ; 92:8, s. 771-794
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Tidskriftsartikel (refereegranskat)abstract
- models are important tools to manage the increasing complexity of system design. The choice of a modeling language for constructing models governs what types of systems can be modeled, and which subsequent design activities can be performed. This is especially true for the area of embedded electronic and cyber-physical system design, which poses several challenging requirements of modeling and design methodologies. This article argues that the Formal System Design (ForSyDe) methodology with the necessary presented extensions fulfills these requirements, and thus qualifies for the design of tomorrow's systems. Based on the theory of models of computation and the concept of process constructors, heterogeneous models are captured in ForSyDe with formal semantics. A refined layer of the formalism is introduced to make its denotational-style semantics easy to implement on top of commonly used imperative languages, and an open-source realization on top of the IEEE standard language SystemC is presented. The introspection mechanism is introduced to automatically export an intermediate representation of the constructed models for further analysis/synthesis by external tools. Flexibility and extensibility of ForSyDe is emphasized by integrating a new timed model of computation without central synchronization, and by providing mechanisms for integrating foreign models, parallel and distributed simulation, modeling adaptive, data-parallel, and non-deterministic systems. A set of ForSyDe features is demonstrated in practice, and compared with similar approaches using a running example and two relevant case studies.
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| 5. |
- Attarzadeh-Niaki, S. -H, et al.
(författare)
-
Automatic construction of models for analytic system-level design space exploration problems
- 2017
-
Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 670-673
-
Konferensbidrag (refereegranskat)abstract
- Due to the variety of application models and also the target platforms used in embedded electronic system design, it is challenging to formulate a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework for automatic construction of system-level DSE problem models based on a coherent, constraint-based representation of system functionality, flexible target platforms, and binding policies. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from different combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. Another potential advantage of this approach is that constructed models can be solved using a variety of standard and ad-hoc solvers and search heuristics.
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| 6. |
- Attarzadeh Niaki, Seyed Hosein, 1984-, et al.
(författare)
-
Automatic Generation of Virtual Prototypes from Platform Templates
- 2015
-
Ingår i: Languages, Design Methods, and Tools for Electronic System Design. - Switzerland : Springer. - 9783319063164 - 9783319063171 ; , s. 147-166
-
Bokkapitel (refereegranskat)abstract
- Virtual Prototypes (VPs) provide an early development platform to embedded software designers when the hardware is not ready yet and allows them to explore the design space of a system, both from the software and architecture perspective. However, automatic generation of VPs is not straightforward because several aspects such as the validity of the generated platforms and the timing of the components needs to be considered. To address this problem, based on a framework which characterizes predictable platform templates, we propose a method for automated generation of VPs which is integrated into a combined design flow consisting of analytic and simulation based design-space exploration. Using our approach the valid TLM-2.0-based simulated VP instances with timing annotation can be generated automatically and used for further development of the system in the design flow. We have demonstrated the potential of our method by designing a JPEG encoder system.
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| 7. |
- Attarzadeh-Niaki, Seyed Hosein, et al.
(författare)
-
Integrating Functional Mock-up units into a formal heterogeneous system modeling framework
- 2015
-
Ingår i: 18th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467380232
-
Konferensbidrag (refereegranskat)abstract
- The Functional Mock-up Interface (FMI) standard defines a method for tool- and platform-independent model exchange and co-simulation of dynamic system models. In FMI, the master algorithm, which executes the imported components, is a timed differential equation solver. This is a limitation for heterogeneous embedded and cyber-physical systems, where models with different time abstractions co-exist and interact. This work integrates FMI into a heterogeneous system modeling and simulation framework as process constructors and co-simulation wrappers. Consequently, each external model communicates with the framework without unnecessary semantic adaptation while the framework provides necessary mechanisms for handling heterogeneity. The presented methods are implemented in the ForSyDe-SystemC modeling framework and tested using a case study.
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| 8. |
- Bonna, Ricardo, et al.
(författare)
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Modeling and Simulation of Dynamic Applications Using Scenario-Aware Dataflow
- 2019
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Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : ASSOC COMPUTING MACHINERY. - 1084-4309 .- 1557-7309. ; 24:5
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Tidskriftsartikel (refereegranskat)abstract
- The tradeoff between analyzability and expressiveness is a key factor when choosing a suitable dataflow model of computation (MoC) for designing, modeling, and simulating applications considering a formal base. A large number of techniques and analysis tools exist for static dataflow models, such as synchronous dataflow. However, they cannot express the dynamic behavior required for more dynamic applications in signal streaming or to model runtime reconfigurable systems. On the other hand, dynamic dataflow models like Kahn process networks sacrifice analyzability for expressiveness. Scenario-aware dataflow (SADF) is an excellent tradeoff providing sufficient expressiveness for dynamic systems, while still giving access to powerful analysis methods. In spite of an increasing interest in SADF methods, there is a lack of formally-defined functional models for describing and simulating SADF systems. This article overcomes the current situation by introducing a functional model for the SADF MoC, as well as a set of abstract operations for simulating it. We present the first modeling and simulation tool for SADF so far, implemented as an open source library in the functional framework ForSyDe. We demonstrate the capabilities of the functional model through a comprehensive tutorial-style example of a RISC processor described as an SADF application, and a traditional streaming application where we model an MPEG-4 simple profile decoder. We also present a couple of alternative approaches for functionally modeling SADF on different languages and paradigms. One of such approaches is used in a performance comparison with our functional model using the MPEG-4 simple profile decoder as a test case. As a result, our proposed model presented a good tradeoff between execution time and implementation succinctness. Finally, we discuss the potential of our formal model as a frontend for formal system design flows regarding dynamic applications.
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| 9. |
- Castañeda Lozano, Roberto, 1986-
(författare)
-
Constraint-Based Register Allocation and Instruction Scheduling
- 2018
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to improve latency or throughput) are central compiler problems. This dissertation proposes a combinatorial optimization approach to these problems that delivers optimal solutions according to a model, captures trade-offs between conflicting decisions, accommodates processor-specific features, and handles different optimization criteria.The use of constraint programming and a novel program representation enables a compact model of register allocation and instruction scheduling. The model captures the complete set of global register allocation subproblems (spilling, assignment, live range splitting, coalescing, load-store optimization, multi-allocation, register packing, and rematerialization) as well as additional subproblems that handle processor-specific features beyond the usual scope of conventional compilers.The approach is implemented in Unison, an open-source tool used in industry and research that complements the state-of-the-art LLVM compiler. Unison applies general and problem-specific constraint solving methods to scale to medium-sized functions, solving functions of up to 647 instructions optimally and improving functions of up to 874 instructions. The approach is evaluated experimentally using different processors (Hexagon, ARM and MIPS), benchmark suites (MediaBench and SPEC CPU2006), and optimization criteria (speed and code size reduction). The results show that Unison generates code of slightly to significantly better quality than LLVM, depending on the characteristics of the targeted processor (1% to 9.3% mean estimated speedup; 0.8% to 3.9% mean code size reduction). Additional experiments for Hexagon show that its estimated speedup has a strong monotonic relationship to the actual execution speedup, resulting in a mean speedup of 5.4% across MediaBench applications.The approach contributed by this dissertation is the first of its kind that is practical (it captures the complete set of subproblems, scales to medium-sized functions, and generates executable code) and effective (it generates better code than the LLVM compiler, fulfilling the promise of combinatorial optimization). It can be applied to trade compilation time for code quality beyond the usual optimization levels, explore and exploit processor-specific features, and identify improvement opportunities in conventional compilers.
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| 10. |
- de Medeiros, Jose. E. G., et al.
(författare)
-
An Algebra for Modeling Continuous Time Systems
- 2018
-
Ingår i: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE. - 9783981926309 ; , s. 861-864
-
Konferensbidrag (refereegranskat)abstract
- Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.
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| 11. |
- Diallo, P. I., et al.
(författare)
-
A formal, model-driven design flow for system simulation and multi-core implementation
- 2015
-
Ingår i: 2015 10th IEEE International Symposium on Industrial Embedded Systems. - : IEEE. - 9781467377119 ; , s. 254-263
-
Konferensbidrag (refereegranskat)abstract
- With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.
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| 12. |
- Fakih, M., et al.
(författare)
-
SAFEPOWER project : Architecture for safe and power-efficient mixed-criticality systems
- 2017
-
Ingår i: Microprocessors and microsystems. - : Elsevier. - 0141-9331 .- 1872-9436. ; 52, s. 89-105
-
Tidskriftsartikel (refereegranskat)abstract
- With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.
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| 13. |
- Gorgen, Ralph, et al.
(författare)
-
CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
- 2016
-
Ingår i: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016). - : IEEE. - 9781509028160 ; , s. 286-293
-
Konferensbidrag (refereegranskat)abstract
- The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.
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| 14. |
- Grüttner, K., et al.
(författare)
-
CONTREX : Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties
- 2017
-
Ingår i: Microprocessors and microsystems. - : Elsevier B.V.. - 0141-9331 .- 1872-9436. ; 51, s. 39-55
-
Tidskriftsartikel (refereegranskat)abstract
- The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).
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| 15. |
- Herrera, F., et al.
(författare)
-
An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems
- 2015
-
Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : ACM Digital Library.
-
Konferensbidrag (refereegranskat)abstract
- Recent work has proposed two-phase joint analytical and simulation-based design space exploration (JAS-DSE) approaches. In such approaches, a first analytical phase relies on static performance estimation and either on exhaustive or heuristic search, to perform a very fast filtering of the design space. Then, a second phase obtains the Pareto solutions after an exhaustive simulation of the solutions found as compliant by the analytical phase. However, the capability of such approaches to find solutions close to the actual Pareto set at a reasonable time cost is compromised by current system complexities. This limitation is due to the fact that such approaches do not support an heuristic exploration on the simulation-based phase. It is not straightforward because in the second phase the heuristic is constrained to consider only the custom set of solutions found in the first phase. This set is in general unconnected and irregularly distributed, which prevents the application of existing heuristics. This paper provides as a solution a novel search heuristic called ARS (Adaptive Random Sampling). The ARS strategy enables the application of heuristic search in the two phases of the JAS-DSE flow, by enabling the application of heuristic in the second phase, regardless the type of performance estimation done at each phase. Moreover, it enables the definition of N-phase DSE flows. The paper shows on an experiment focused on predictable multi-core systems how this enhanced JAS-DSE is capable to find more efficient solutions and to tune the trade-off between exploration time and accuracy in finding actual Pareto solutions.
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| 16. |
- Herrera, Fernando, et al.
(författare)
-
An extensible infrastructure for modeling and time analysis of predictable embedded systems
- 2015
-
Ingår i: Forum on Specification and Design Languages. - : IEEE Computer Society. - 9791092279078
-
Konferensbidrag (refereegranskat)abstract
- Efficient design of predictable systems on top of multiprocessor-based architectures is challenging. It demands an integration effort to support system models relying on Models-of-Computation (MoC) theory, supporting real-time (RT) analysis and electronic system-level (ESL) design techniques. This paper presents a SystemC-based framework for modelling and time analysis of predictable embedded systems which aims such an integration. The framework has features for system-level design and research of predictable systems. Moreover, the framework is extensible, to enable experts from different communities to explore and assess their contributions, e.g. new schedulers, schedulability analyses, and predictable platform components, without having to rely on a physical platform.
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| 17. |
- Herrera, Fernando, et al.
(författare)
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Combining analytical and simulation-based design space exploration for efficient time-critical and mixed-criticality systems
- 2015
-
Ingår i: Forum on Specification and Design Languages, FDL 2013. - Cham : Springer International Publishing. - 9783319063164 ; , s. 167-188
-
Konferensbidrag (refereegranskat)abstract
- In the context of the design on time-critical systems, analytical models with worst case workloads are used to identify safe solutions that guarantee hard timing constraints. However, the focus on the worst case often leads to unnecessarily pessimistic and inefficient solutions, in particular for mixed-critical systems. To overcome the situation, the paper proposes a novel design flow integrating analytical and simulation-based Design Space Exploration (DSE). This combined approach is capable to find more efficient design solutions, without sacrificing timing guarantees. For it, a first analytical DSE phase obtains a set of solutions compliant with the critical time constraints. Search of the Pareto optimum solutions is done among this set, but it is delegated to a second simulation-based search. The simulation-based search enables more accurate estimations, and the consideration of a specific (or an average-case) scenario. The chapter shows that this can lead to different Pareto sets which reflect improved design decisions with respect to a pure analytical DSE approach, and which are found faster than through a pure simulation-based DSE approach. This is illustrated through an accompanying example and a proof-of-concept implementation of the proposed DSE flow.
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| 18. |
- Hjort Blindell, Gabriel, et al.
(författare)
-
Synthesizing Code for GPGPUs from abstract formal models
- 2016
-
Ingår i: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014. - Cham : Springer. ; , s. 115-134
-
Konferensbidrag (refereegranskat)abstract
- Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this chapter a novel software synthesis tool—called f2cc—which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28× speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.
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| 19. |
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| 20. |
- Kehoe, Laura, et al.
(författare)
-
Make EU trade with Brazil sustainable
- 2019
-
Ingår i: Science. - : American Association for the Advancement of Science (AAAS). - 0036-8075 .- 1095-9203. ; 364:6438, s. 341-
-
Tidskriftsartikel (övrigt vetenskapligt/konstnärligt)
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| 21. |
- Khalilzad, Nima, 1986-, et al.
(författare)
-
A modular design space exploration framework for multiprocessor real-time systems
- 2016
-
Ingår i: Forum on Specification and Design Languages. - : IEEE. - 9791092279177
-
Konferensbidrag (refereegranskat)abstract
- Embedded system designers often face a large number of design alternatives when designing complex systems. A designer must select an alternative which satisfies application constraints (e.g. timing requirements) while optimizing system level objectives such as overall energy consumption. The size of design space is often very large giving rise to the need for systematic Design Space Exploration (DSE) methods. In this paper we address the DSE problem for real-time applications that belong to two different domains: (i) streaming applications modeled using the synchronous dataflow graphs; (ii) feedback control tasks modeled using the periodic task model. We consider a heterogeneous multiprocessor platform in which processors communicate through a predictable bus architecture. We present our DSE tool in which the DSE problem is modeled as a constraint satisfaction problem, and it is solved using a constraint programming solver. This approach provides a modular framework in which different constraints such as deadline, throughput and energy consumption can easily be plugged depending on the system being designed.
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| 22. |
- Lenz, Alina, et al.
(författare)
-
SAFEPOWER project : Architecture for Safe and Power-Efficient Mixed-Criticality Systems
- 2016
-
Ingår i: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016). - : IEEE. - 9781509028160 ; , s. 294-300
-
Konferensbidrag (refereegranskat)abstract
- With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible not regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised, because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER(1) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality real-time systems (MCRTES). This paper will introduce the requirements that a power efficient SoC has to meet and the challenges such a SoC has to overcome.
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| 23. |
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| 24. |
- Navas, Byron, 1969-
(författare)
-
Cognitive and Self-Adaptive SoCs with Self-Healing Run-Time-Reconfigurable RecoBlocks
- 2015
-
Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
- In contrast to classical Field-Programmable Gate Arrays (FPGAs), partial and run-time reconfigurable (RTR) FPGAs can selectively reconfigure partitions of its hardware almost immediately while it is still powered and operative. In this way, RTR FPGAs combine the flexibility of software with the high efficiency of hardware. However, their potential cannot be fully exploited due to the increased complexity of the design process, and the intricacy to generate partial reconfigurations. FPGAs are often seen as a single auxiliary area to accelerate algorithms for specific problems. However, when several RTR partitions are implemented and combined with a processor system, new opportunities and challenges appear due to the creation of a heterogeneous RTR embedded system-on-chip (SoC).The aim of this thesis is to investigate how the flexibility, reusability, and productivity in the design process of partial and RTR embedded SoCs can be improved to enable research and development of novel applications in areas such as hardware acceleration, dynamic fault-tolerance, self-healing, self-awareness, and self-adaptation. To address this question, this thesis proposes a solution based on modular reconfigurable IP-cores and design-and-reuse principles to reduce the design complexity and maximize the productivity of such FPGA-based SoCs. The research presented in this thesis found inspiration in several related topics and sciences such as reconfigurable computing, dependability and fault-tolerance, complex adaptive systems, bio-inspired hardware, organic and autonomic computing, psychology, and machine learning.The outcome of this thesis demonstrates that the proposed solution addressed the research question and enabled investigation in initially unexpected fields. The particular contributions of this thesis are: (1) the RecoBlock SoC concept and platform with its flexible and reusable array of RTR IP-cores, (2) a simplified method to transform complex algorithms modeled in Matlab into relocatable partial reconfigurations adapted to an improved RecoBlock IP-core architecture, (3) the self-healing RTR fault-tolerant (FT) schemes, especially the Upset-Fault-Observer (UFO) that reuse available RTR IP-cores to self-assemble hardware redundancy during runtime, (4) the concept of Cognitive Reconfigurable Hardware (CRH) that defines a development path to achieve self-adaptation and cognitive development, (5) an adaptive self-aware and fault-tolerant RTR SoC that learns to adapt the RTR FT schemes to performance goals under uncertainty using rule-based decision making, (6) a method based on online and model-free reinforcement learning that uses a Q-algorithm to self-optimize the activation of dynamic FT schemes in performance-aware RecoBlock SoCs.The vision of this thesis proposes a new class of self-adaptive and cognitive hardware systems consisting of arrays of modular RTR IP-cores. Such a system becomes self-aware of its internal performance and learns to self-optimize the decisions that trigger the adequate self-organization of these RTR cores, i.e., to create dynamic hardware redundancy and self-healing, particularly while working in uncertain environments.
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| 25. |
- Navas, Byron, et al.
(författare)
-
Reinforcement Learning Based Self-Optimization of Dynamic Fault-Tolerant Schemes in Performance-Aware RecoBlock SoCs
- 2015
-
Rapport (övrigt vetenskapligt/konstnärligt)abstract
- Partial and run-time reconfiguration (RTR) technology has increased the range of opportunities and applications in the design of systems-on-chip (SoCs) based on Field-Programmable Gate Arrays (FPGAs). Nevertheless, RTR adds another complexity to the design process, particularly when embedded FPGAs have to deal with power and performance constraints uncertain environments. Embedded systems will need to make autonomous decisions, develop cognitive properties such as self-awareness and finally become self-adaptive to be deployed in the real world. Classico-line modeling and programming methods are inadequate to cope with unpredictable environments. Reinforcement learning (RL) methods have been successfully explored to solve these complex optimization problems mainly in workstation computers, yet they are rarely implemented in embedded systems. Disruptive integration technologies reaching atomic-scales will increase the probability of fabrication errors and the sensitivity to electromagnetic radiation that can generate single-event upsets (SEUs) in the configuration memory of FPGAs. Dynamic FT schemes are promising RTR hardware redundancy structures that improve dependability, but on the other hand, they increase memory system traffic. This article presents an FPGA-based SoC that is self-aware of its monitored hardware and utilizes an online RL method to self-optimize the decisions that maintain the desired system performance, particularly when triggering hardware acceleration and dynamic FT schemes on RTR IP-cores. Moreover, this article describes the main features of the RecoBlock SoC concept, overviews the RL theory, shows the Q-learning algorithm adapted for the dynamic fault-tolerance optimization problem, and presents its simulation in Matlab. Based on this investigation, the Q-learning algorithm will be implemented and verified in the RecoBlock SoC platform.
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| 26. |
- Navas, Byron, et al.
(författare)
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Towards cognitive reconfigurable hardware : Self-aware learning in RTR fault-tolerant SoCs
- 2015
-
Ingår i: Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781467379427
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Konferensbidrag (refereegranskat)abstract
- Traditional embedded systems are evolving into power-and-performance-domain self-aware intelligent systems in order to overcome complexity and uncertainty. Without human control, they need to keep operative states in applications such as drone-based delivery or robotic space landing. Nowadays, the partial and run-time reconfiguration (RTR) of FPGA-based Systems-on-chip (SoC) can enable dynamic hardware acceleration or self-healing structures, but this conversely increases system-memory traffic. This paper introduces the basis of cognitive reconfigurable hardware and presents the design of an FPGA-based RTR SoC that becomes conscious of its monitored hardware and learns to make decisions that maintain a desired system performance, particularly when triggering hardware acceleration and dynamic fault-tolerant (FT) schemes on RTR cores. Self-awareness is achieved by evaluating monitored metrics in critical AXI-cores, supported by hardware performance counters. We suggest a reinforcement-learning algorithm that helps the system to search out when and which reconfigurable FT-scheme can be triggered. Executing random sequences of an embedded benchmark suite simulates unpredictability and bus traffic. The evaluation shows the effectiveness and implications of our approach.
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| 27. |
- Paone, E., et al.
(författare)
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Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints
- 2015
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Ingår i: Proceedings -Design, Automation and Test in Europe, DATE. - New Jersey : IEEE conference proceedings. - 9783981537048 ; , s. 736-741
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Konferensbidrag (refereegranskat)abstract
- When targeting an OpenCL application to platforms with multiple heterogeneous accelerators, task tuning and mapping have to cope with device-specific constraints. To address this problem, we present an innovative design flow for the customization and performance optimization of OpenCL applications on heterogeneous parallel platforms. It consists of two phases: 1) a tuning phase that optimizes each application kernel for a given platform and 2) a task-mapping phase that maximizes the overall application throughput by exploiting concurrency in the application task graph. The tuning phase is suitable for customizing parameterized OpenCL kernels considering device-specific constraints. Then, the mapping phase improves task-level parallelism for multi-device execution accounting for the overhead of memory transfers - overheads implied by multiple OpenCL contexts for different device vendors. Benefits of the proposed design flow have been assessed on a stereo-matching application targeting two commercial heterogeneous platforms.
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| 28. |
- Rosvall, Kathrin, et al.
(författare)
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Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors
- 2018
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Konferensbidrag (refereegranskat)abstract
- System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.
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| 29. |
- Rosvall, Kathrin, et al.
(författare)
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Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms
- 2018
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Ingår i: ACM Transactions on Design Automation of Electronic Systems. - : Association for Computing Machinery (ACM). - 1084-4309 .- 1557-7309. ; 23:2
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Tidskriftsartikel (refereegranskat)abstract
- Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based on Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none of the available CP approaches consider the tradeoff between throughput and buffer requirements or throughput and power consumption. This article integrates tradeoff awareness into the CP model and introduces a two-step solving approach that utilizes the advantages of heuristics, while still keeping the completeness property of CP. With a number of experiments considering several streaming applications and different platform models, the article illustrates not only the efficiency of the presented model but also its suitability for solving different problems with various combinations of performance constraints.
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| 30. |
- Rosvall, Kathrin, et al.
(författare)
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Throughput propagation in constraint-based design space exploration for mixed-criticality systems
- 2017
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Ingår i: ACM International Conference Proceeding Series. - New York, NY, USA : Association for Computing Machinery (ACM). - 9781450348409
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Konferensbidrag (refereegranskat)abstract
- When designing complex mixed-critical systems on multiprocessor platforms, a huge number of design alternatives has to be evaluated. Therefore, there is a need for tools which systematically find and analyze the ample alternatives and identify solutions that satisfy the design constraints. The recently proposed design space exploration (DSE) tool DeSyDe uses constraint programming (CP) to find implementations with performance guarantees for multiple applications with potentially mixed-critical design constraints on a shared platform. A key component of the DeSyDe tool is its throughput analysis component, called a throughput propagator in the context of CP. The throughput propagator guides the exploration by evaluating each design decision and is therefore executed excessively throughout the exploration. This paper presents two throughput propagators based on different analysis methods for DeSyDe. Their performance is evaluated in a range of experiments with six different application graphs, heterogeneous platform models and mixed-critical design constraints. The results suggest that the MCR throughput propagator is more efficient.
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| 31. |
- Sander, Ingo, 1964-, et al.
(författare)
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ForSyDe : System design using a functional language and models of computation
- 2017
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Ingår i: Handbook of Hardware/Software Codesign. - Dordrecht : Springer Netherlands. - 9789401772679 - 9789401772662 ; , s. 99-140
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Bokkapitel (övrigt vetenskapligt/konstnärligt)abstract
- The ForSyDe methodology aims to push system design to a higher level of abstraction by combining the functional programming paradigm with the theory of Models of Computation (MoCs). A key concept of ForSyDe is the use of higher-order functions as process constructors to create processes. This leads to well-defined and well-structured ForSyDe models and gives a solid base for formal analysis. The book chapter introduces the basic concepts of the ForSyDe modeling framework and presents libraries for several MoCs and MoC interfaces for the modeling of heterogeneous systems, including support for the modeling of run-time reconfigurable processes. The formal nature of ForSyDe enables transformational design refinement using both semantic-preserving and nonsemantic-preserving design transformations. The chapter also introduces a general synthesis concept based on process constructors, which is exemplified by means of a hardware synthesis tool for synchronous ForSyDe models. Most examples in the chapter are modeled with the Haskell version of ForSyDe. However, to illustrate that ForSyDe is languageindependent, the chapter also contains a short overview of SystemC-ForSyDe.
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| 32. |
- Ungureanu, George, et al.
(författare)
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A layered formal framework for modeling of cyber-physical systems
- 2017
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Ingår i: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9783981537093 ; , s. 1715-1720
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Konferensbidrag (refereegranskat)abstract
- Designing cyber-physical systems is highly challenging due to its manifold interdependent aspects such as composition, timing, synchronization and behavior. Several formal models exist for description and analysis of these aspects, but they focus mainly on a single or only a few system properties. We propose a formal composable framework which tackles these concerns in isolation, while capturing interaction between them as a single layered model. This yields a holistic, fine-grained, hierarchical and structured view of a cyber-physical system. We demonstrate the various benefits for modeling, analysis and synthesis through a typical example.
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| 33. |
- Ungureanu, George, et al.
(författare)
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Bridging Discrete and Continuous Time Models with Atoms
- 2018
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Ingår i: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE). - : IEEE. - 9783981926309 ; , s. 277-280
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Konferensbidrag (refereegranskat)abstract
- Recent trends in replacing traditionally digital components with analog counterparts in order to overcome physical limitations have led to an increasing need for rigorous modeling and simulation of hybrid systems. Combining the two domains under the same set of semantics is not straightforward and often leads to chaotic and non-deterministic behavior due to the lack of a common understanding of aspects concerning time. We propose an algebra of primitive interactions between continuous and discrete aspects of systems which enables their description within two orthogonal layers of computation. We show its benefits from the perspective of modeling and simulation, through the example of an RC oscillator modeled in a formal framework implementing this algebra.
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| 34. |
- Ungureanu, George, et al.
(författare)
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Formal design, co-simulation and validation of a radar signal processing system
- 2019
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Ingår i: Proceedings of the 2019 Forum on Specification and Design Languages, FDL 2019. - : Institute of Electrical and Electronics Engineers Inc.. - 9781728141138
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Konferensbidrag (refereegranskat)abstract
- With the ever increasing complexity in safety-critical and performance-demanding application domains such as automotive and avionics, the costs of designing, producing and especially testing systems does not scale well for the next generation of applications. One example is the active electronically scanned array (AESA) antenna signal processing chain, which is currently out-of-reach from consumer products but rather part of a few exclusive hi-tech appliances. To cope with the associated complexity of such systems, we propose a design flow starting from a high-level formal modeling language which captures and exposes important design properties to enable their systematic exploitation for the purpose of simulation, analysis and synthesis towards cost-efficient implementations. We demonstrate the capabilities of this approach by providing a compact yet expressive description of the AESA signal processing chain, generate automatic test-cases to verify the conformity of model with design specifications, synthesize a part of it to VHDL and co-simulate the generated artifact to validate its correctness.
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