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Träfflista för sökning "WFRF:(Seger Johan) srt2:(2005-2009)"

Sökning: WFRF:(Seger Johan) > (2005-2009)

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1.
  • Olsen, Sarah H., et al. (författare)
  • Control of self-heating in thin virtual substrate strained Si MOSFETs
  • 2006
  • Ingår i: IEEE Transactions on Electron Devices. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9383 .- 1557-9646. ; 53:9, s. 2296-2305
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents the first results and analysis of strained Si n-channel MOSFETs fabricated on thin SiGe virtual substrates. Significant improvements in electrical performance are demonstrated compared with Si control devices. The impact of SiGe device self-heating is compared for strained Si MOSFETs fabricated on thin and thick virtual substrates. This paper demonstrates that by using high-quality thin virtual substrates,,the compromised performance enhancements commonly observed in short-gate-length MOSFETs and high-bias conditions due to self-heating in conventional thick virtual substrate devices are eradicated. The devices were fabricated with a 2.8-nm gate oxide and included NiSi to reduce the parasitic series resistance. The strained layers grown on the novel substrates comprising 20% Ge did not relax during fabrication. Good ON-state performance, OFF-state performance, and cross-wafer uniformity are demonstrated. The results show that thin virtual substrates have the potential to circumvent the major issues associated with conventional virtual substrate technology. A promising solution for realizing high-performance strained Si devices suitable for a wide range of applications is thus presented.
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2.
  • Seger, Johan, 1975- (författare)
  • Interaction of Ni with SiGe for electrical contacts in CMOS technology
  • 2005
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
    • This thesis investigates the reactive formation of Ni mono-gernanosilicide, NiSi1-uGeu, for contact metallization of future CMOS devices where Si1-xGex can be present in the gate, source and drain of a MOSFET. Although the investigation has been pursued with a strong focus on materials aspects, issues related to process integration in MOSFETs both on conventional bulk Si and ultra-thin body SOI have been taken into consideration. The thesis work has taken a balance between experimental studies and theoretical calculations. The interaction between Ni films and Si1-xGex substrates, polycrystalline (poly) as in the gate or single-crystal (sc) as in the source/drain, leads to the formation of a ternary solid solution NiSi1-uGeu with the MnP structure in a wide range of temperature from 450 to 850oC. A linear variation of the lattice parameters of the NiSi1-uGeu with u is determined. A number of key observations are made: (1) the agglomeration of NiSi1-uGeu on Si1-xGex at a lower temperature compared to that of NiSi on Si, (2) the absence of NiSi2 up to 850 oC when Ge is present, and (3) a substantial Ge out-diffusion from the NiSi1-xGex and a precipitation of Ge-richer SiGe around the NiSi1-uGeu grains. These observations are interpreted referring to the ternary phase diagram for the Ni-Si-Ge system presented in this work. Possible factors influencing the morphological stability of NiSi1-uGeu films on Si1-xGex are discussed: (1) mechanical strain in the epitaxial Si1-xGex, (2) the favorable formation of NiSi at the expense of NiGe, (3) grain growth in poly-Si1-xGex, and (4) grain grooving in NiSi1-uGeu on sc-Si1-xGex. Energetically, the former two factors have been found to play a comparable, yet major role in the morphological instability of NiSi1-uGeu. The inter-diffusion of Si and Ge in NiSi1-uGeu and Si1-xGex provides the kinetic pathway for the morphological evolution. On Si1-xGex epitaxially grown on Si(100), a strong preferential orientation of the resulting NiSi1-uGeu film is found; NiSi films formed on Si show no specific film texturing. Furthermore, layer sequence and layer thickness of Si/SiGe or SiGe/Si are found to strongly affect the film texture in the resulting NiSi1-uGeu. Epitaxy of NiSi on NiSi1-uGeu, and vice versa, occurs across the compositional boundary, which confirms Ni as the dominant diffusion species during germanosilicide formation. The presence of Ge reduces the contact resistivity for NiSi1-uGeu on p-tyep Si1-xGex, as expected. For poly-Si1-xGex doped by B to 1020cm-3, a contact resistivity of 9x10-8 Ωcm2, 5 times lower than for the corresponding NiSi/Si contact, is obtained. On n-type Si1-xGex doped by As to 1020 cm-3, the opposite is true regarding the effect of Ge and a contact resistivity of 2x10-5 Ωcm2, 20 times higher than for the corresponding NiSi/Si contact, is obtained. When formed in the source/drain regions of a MOSFET fabricated on ultra-thin body SOI, a severe lateral growth of NiSi and Ni2Si into the channel region is revealed if the initial Ni thickness is too thick and if the silicidation conditions are not carefully controlled. This leads to a Schottky contact S/D MOSFET due to the consumption of the entire source/drain. In order to realize a low source/drain resistance for MOSFETs on ultra-thin SOI, satisfying the Roadmap recommendation for the 45-nm technology node, simplified calculations have been performed and an elevated source/drain structure is clearly shown to be advantageous.
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3.
  • Seger, Johan, et al. (författare)
  • Lateral encroachment of Ni-silicides in the source/drain regions on ultrathin silicon-on-insulator
  • 2005
  • Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 86:25
  • Tidskriftsartikel (refereegranskat)abstract
    • Lateral growth of Ni silicide towards the channel region of metal-oxide-semiconductor transistors (MOSFETs) fabricated on ultrathin silicon-on-insulator (SOI) is characterized using SOI wafers with a 20-nm-thick surface Si layer. With a 10-nm-thick Ni film for silicide formation, p-channel MOSFETs displaying ordinary device characteristics with silicided p(+) source/drain regions were demonstrated. No lateral growth of NiSix under gate isolation spacers was found according to electron microscopy. When the Ni film was 20 nm thick, Schottky contact source/drain MOSFETs showing typical ambipolar characteristics were obtained. A severe lateral encroachment of NiSix into the channel region leading to an increased gate leakage was revealed, while no detectable voiding at the silicide front towards the Si channel was observed.
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4.
  • von Haartman, Martin, et al. (författare)
  • Low-frequency noise in SiGe channel pMOSFETs on ultra-thin body SOI with Ni-silicided source/drain
  • 2005
  • Ingår i: Noise and Fluctuations. - : AIP. ; , s. 307-310
  • Konferensbidrag (refereegranskat)abstract
    • Thelow-frequency noise in buried SiGe channel pMOSFETs fabricated on ultra-thinbody silicon-on-insulator (SOI) substrates is investigated. The total thickness ofthe Si/SiGe/Si body structure, which is fully depleted (FD), is20 nm. The low-frequency noise properties are compared with FDSOI pMOSFETs with a 20 nm Si body. The effectof the Ni-silicide used in the Source/Drain were also studied,especially the case of Schottky-Barrier (SB) MOSFETs when the Ni-silicideis formed at the edges of the channel.
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5.
  • Östling, Mikael, et al. (författare)
  • Novel integration concepts for sige-based rf-MOSFETs
  • 2005
  • Ingår i: Proc. Electrochem. Soc.. ; , s. 270-284
  • Konferensbidrag (refereegranskat)abstract
    • An overview of critical integration issues for future generation rf-MOSFETs is presented. The process requirements and implementation of selective epitaxy for the source and drain regions is given. In-situ doping of highly boron doped recessed SiGe S/D is demonstrated. Channel region engineering is discussed and 50 nm strained SiGe pMOSFETs are demonstrated. Implementation of high-κ gate dielectrics is presented and device performance is demonstrated for surface channel MOSFETs with a gate stack based on ALD-formed HfO2/Al 2O3. Low frequency noise properties for those devices are analyzed. Contact metallization issues are critical for ultra scaled devices and here the implementation of NiSi on SiGe(C) regions as well as on ultra thin body SOI MOSFETs are presented. Finally, a spacer pattering technology using optical lithography to fabricate sub-50 nm high-frequency MOSFETs is demonstrated.
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