| 1. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Compensation Technique for Two-Stage Differential OTAs
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 61:8, s. 594-598
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Tidskriftsartikel (refereegranskat)abstract
- In this paper a frequency compensation method for operational transconductance amplifiers is proposed, which poses no power overhead compared to Miller compensation, while improving the 3dB bandwidth, the unity gain frequency and the slew rate. The technique employees positive feedback to introduce an extra left half plane zero to cancel a pole.The phase margin shows good robustness against process and temperature variations. The proposed technique poses no design constraints on the transconductance or capacitor values which makes it attractive for low power applications with low area overhead.
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| 2. |
- Abdulaziz, Mohammed, et al.
(författare)
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A Linearization Technique for Differential OTAs
- 2017
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 64:9, s. 1002-1006
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Tidskriftsartikel (refereegranskat)abstract
- This brief presents an operational transconductance amplifier (OTA) linearization technique that is applied to a low-noise amplifier (LNA) and an OTA-C filter. Simulations show the effectiveness of the proposed technique on the LNA, whose noise and gain performance remain unaffected while the linearity is significantly improved. Measurements of the 80-MHz fourth order Butterworth OTA-C filter are also presented. It is implemented using six OTAs instead of eight, thus reducing the power consumption and area. The filter is implemented in 65-nm low-power CMOS, with a core area of 0.05 mm 2 and consumes 12.6 mA from 1.2 V supply. The measured in-band noise voltage is below 42 nV/ Hz‾‾‾√ , and the measured third order intercept point improvement using OTA linearization is up to 17 dB in-band and about 3 dB out-of-band. Supply and temperature variation measurements on three samples show that the linearization is effective without a need for bias adjustment.
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| 3. |
- Afzal, Nadeem, et al.
(författare)
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Reducing Complexity and Power of Digital Multibit Error-Feedback Delta Sigma Modulators
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:9, s. 641-645
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we propose how the hardware complexity of arbitrary-order digital multibit error-feedback delta-sigma modulators can be reduced. This is achieved by splitting the combinatorial circuitry of the modulators into two parts, i.e., one producing the modulator output and another producing the error signal fed back. The part producing modulator output is removed by utilizing a unit-element-based digital-to-analog converter. To illustrate the reduced complexity and power consumption, we compare the synthesized results with those of conventional structures. Fourth-order modulators implemented with the proposed technique use up to 26% less area compared with conventional implementations. Due to the area reduction, the designs consume up to 33% less dynamic power. Furthermore, it can operate at a frequency 100 MHz higher than that of the conventional.
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| 4. |
- Akhlaghpasand, Hossein, et al.
(författare)
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Jamming Suppression in Massive MIMO Systems
- 2020
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 1549-7747 .- 1558-3791. ; 67:1, s. 182-186
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Tidskriftsartikel (refereegranskat)abstract
- In this brief, we propose a framework for protecting the uplink transmission of a massive multiple-input multiple-output (mMIMO) system from a jamming attack. Our framework includes a novel minimum mean-squared error-based jamming suppression (MMSE-JS) estimator for channel training and a linear zero-forcing jamming suppression (ZFJS) detector for uplink combining. The MMSE-JS exploits some intentionally unused pilots to reduce the pilot contamination caused by the jammer. The ZFJS suppresses the jamming interference during the detection of the legitimate users' data symbols. The proposed framework is implementable, since the complexities of computing the MMSE-JS and the ZFJS are linear (not exponential) with respect to the number of antennas at the base station and can be fabricated using 28-nm fully depleted silicon on insulator technology and for the mMIMO systems. Our analysis shows that the jammer cannot dramatically affect the performance of an mMIMO system equipped with the combination of MMSE-JS and ZFJS. Numerical results confirm our analysis.
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| 5. |
- Andersson, Martin, et al.
(författare)
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DT Modeling of Clock Phase Noise Effects in LP CT Delta-Sigma ADCs with RZ Feedback
- 2009
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 56:7, s. 530-534
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Tidskriftsartikel (refereegranskat)abstract
- The performance of continuous-time (CT) Delta Sigma modulators is limited by their sensitivity to clock phase noise (PN). The clock PN-induced in-band noise (IBN) is dependent on the magnitude and frequency of both the desired in-band signals and the out-of-band signals, as well as the shape of the clock PN spectrum. This brief presents a discrete-time (DT) model of the dominant clock PN-induced errors. It enables fast and accurate simulations of the clock PN effects with arbitrary input signals, PN spectra, and noise-transfer functions. The model has been verified by CT simulations and measurements on a second-order low-pass CT Delta Sigma modulator with return-to-zero feedback. The flexibility and usefulness of the DT model are demonstrated, and the two dominant clock PN effects are compared by means of simulations with orthogonal frequency-division multiplexing input signals and various PN specifications.
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| 6. |
- Andersson, Niklas, et al.
(författare)
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A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:10, s. 773-777
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Tidskriftsartikel (refereegranskat)abstract
- A new Vernier time-to-digital converter (TDC) architecture using a delay line and a chain of delay latches is proposed. The delay latches replace the functionality of one delay chain and the sample register commonly found in Vernier converters, hereby enabling power and hardware efficiency improvements. The delay latches can be implemented using either standard or full custom cells, allowing the architecture to be implemented in field-programmable gate arrays, digital synthesized application-specific integrated circuits, or in full custom design flows. To demonstrate the proposed concept, a 7-bit Vernier TDC has been implemented in a standard 65-nm CMOS process with an active core size of 33 mu m x 120 mu m. The time resolution is 5.7 ps with a power consumption of 1.75 mW measured at a conversion rate of 100 MS/s.
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| 7. |
- Andreani, Pietro
(författare)
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Some Results on Oscillation Stability in Multi-Mode Harmonic Oscillators
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:3, s. 860-864
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Tidskriftsartikel (refereegranskat)abstract
- We study the stability of oscillation in two different multi-mode harmonic oscillators by means of Barkhausen’s criterion, involving a minimum of mathematical machinery in favor of a more intuitive, circuit-based approach. The results of the theoretical analysis match very closely those obtained through transient simulations, confirming occasionally surprising outcomes of the latter.
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| 8. |
- Angelov, Pavel, et al.
(författare)
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A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
- 2014
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Ingår i: IEEE Transactions on Circuits and Systems - II - Express Briefs. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-7747 .- 1558-3791. ; 61:11, s. 860-864
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Tidskriftsartikel (refereegranskat)abstract
- We present the design of an integrated multiplexer and a dc clamp for the input analog interface of a high-speed video digitizer in the 1.1-V 65-nm complementary metal-oxide-semiconductor process. The ac-coupled video signal is dc restored using a novel all-digital current-mode charge pump. An eight-input multiplexer is realized with T-switches, each containing two series-connected bootstrapped switches. A T-switchs grounding branch is merged with the pull-down end of the clamping charge pump. An adaptive digital feedback loop encompassing a video analog-to-digital converter (ADC) controls the clamp charge pump. The bootstrapped switches have been adapted to suit the video environment, allowing on-the-fly recharging. The varying ON-resistance of the conventional bootstrapped switch is utilized to linearize the multiplexer response by canceling the effect of the nonlinear load capacitance contributed by the clamp transistors. Under worst case conditions, the multiplexer maintains a 62-85-dB spurious-free dynamic range over a range of known input video frequencies, and it reduces the second-order harmonic component upon optimization. The dc clamp provides 12-bit precision over the full range of the video ADC and can set the dc at the target level for at most 194 video lines.
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| 9. |
- Behmanesh, Baktash, et al.
(författare)
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On the Calculation and Simulation of Loop Gain in Feedback Circuits
- 2023
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 70:11, s. 4033-4037
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Tidskriftsartikel (refereegranskat)abstract
- We derive the expression of the loop gain in a circuit containing one or more feedback loops, where the transfer functions building the expression are found by means of a few AC analyses on the circuit. No approximations or assumptions on the nature of the loop or of the impedances therein contained are necessary. While hand calculations are certainly possible in the case of simpler circuits, the method is especially suitable for deployment in an analog circuit simulator environment.
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| 10. |
- Bevilacqua, Andrea, et al.
(författare)
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Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
- 2012
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Ingår i: IEEE Transactions on Circuits and Systems II: Express Briefs. - 1549-7747. ; 59:1, s. 20-24
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Tidskriftsartikel (refereegranskat)abstract
- The theoretical phase noise performance of a tuned-input tuned-output (TITO) oscillator is analyzed with a rigorous approach, which yields a compact closed-form phase noise equation that is dependent only on the value of the circuit components and current consumption of the oscillator. A straightforward comparison with the more commonly used differential LC-tank oscillator shows that the latter is in fact superior to the TITO oscillator, at least if the oscillator behavior is not too distant from the ideal behavior considered in the analysis. Phase noise simulations match admirably the theoretical results.
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