| 1. |
- Akgun, OmerCan, et al.
(författare)
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High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
- 2012
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Ingår i: IEEE Transactions on Biomedical Circuits and Systems. - 1932-4545. ; 6:1, s. 15-27
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to be operated in the sub-threshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle. The application of the model is demonstrated by exploring the energy efficiency of pipelining, retiming and register balancing. Simulation results, which are obtained during a fraction of SPICE simulation time, are validated by measurements on a wavelet based cardiac event detector that was fabricated in 65 nm low-leakage high-threshold technology. The mean of the absolute modeling error is calculated as 5.2 %, with a standard deviation of 6.6% over the measurement points. The cardiac event detector dissipates 0.88 pJ/sample at a supply voltage of 320mV.
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| 2. |
- Al-Obaidi, Mohammed, et al.
(författare)
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Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
- 2013
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Ingår i: 2013 IEEE International Symposium on Circuits and Systems (ISCAS). - 2158-1525 .- 0271-4310. - 9781467357623 - 9781467357609 ; , s. 293-296
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Konferensbidrag (refereegranskat)abstract
- In LTE base-stations, RoHC is a processingintensive algorithm that may limit the system from serving a large number of users when it is used to compress the VoIP packets of mobile traffic. In this paper, a hardware-software and a full-hardware solution are proposed to accelerate the RoHC compression algorithm in LTE base-stations and enhance the system throughput and capacity. Results for both solutions are discussed and compared with respect to design metrics like throughput, capacity, power consumption, and hardware resources. This comparison is instrumental in taking architectural level trade-off decisions in-order to meet the present day requirements and also be ready to support a future evolution. In terms of throughput, a gain of 20% (6250 packets/sec) is achieved in the HW-SW implementation by accelerating the Cyclic Redundancy Check (CRC) and the Least Significant Bit (LSB) encoding in hardware. The full-HW implementation leads to a throughput of 45 times (244000 packets/sec) compared to the SW-Only implementation. The full-HW solution consumes more Adaptive Look-Up Tables (7477 ALUTs) compared to the HW-SW solution (2614 ALUTs) when synthesized on Altera’s Arria II GX FPGA.
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| 3. |
- Anderson, John B, et al.
(författare)
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Faster-Than-Nyquist Signaling
- 2013
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Ingår i: Proceedings of the IEEE. - 0018-9219. ; 101:8, s. 1817-1830
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we survey Faster-than-Nyquist (FTN) signaling, an extension of ordinary linear modulation in which the usual data bearing pulses are simply sent faster, and consequently are no longer orthogonal. Far from a disadvantage, this innovation can transmit up to twice the bits as ordinary modulation at the same bit energy, spectrum, and error rate. The method is directly applicable to orthogonal frequency division multiplex (OFDM) and quadrature amplitude modulation (QAM) signaling. Performance results for a number of practical systems are presented. FTN signaling raises a number of basic issues in communication theory and practice. The Shannon capacity of the signals is considerably higher.
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| 5. |
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| 6. |
- Berkeman, Anders, et al.
(författare)
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A configurable divider using digit recurrence
- 2003
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Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - 2158-1525 .- 0271-4310. ; 5, s. 333-336
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Konferensbidrag (refereegranskat)abstract
- The division operation is essential in many digital signal processing algorithms. For a hardware implementation, the requirements and constraints on the divider circuit differ significantly with different applications. Therefore, it is not possible to design one divider component having optimal performance and cost for all target applications. Instead, the presented divider has a modular architecture, based on instantiation of small efficient divider sub-blocks. The configuration of the divider architecture is set by a number of parameters controlling wordlength, number of quotient bits, number of clock cycles per operation, and fixed or floating point operation. Digit recurrence algorithms with carry save arithmetic and on-the-fly two's complement output quotient conversion are used to make the sub-blocks small, fast and power efficient, The modularity gives the designer freedom to elaborate different parameters to explore the design space. Two applications using the proposed divider are presented. Furthermore, an example divider circuit has been fabricated and performance measurements are included.
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| 7. |
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| 8. |
- Berkeman, Anders, et al.
(författare)
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A low logic depth complex multiplier
- 1998
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Ingår i: ; , s. 204-207
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Konferensbidrag (refereegranskat)abstract
- A complex multiplier has been designed for use in a pipelined fast fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input to output delay as short as possible. A new architecture based on distributed arithmetic and Wallace-trees has been developed and is compared to a previous multiplier realized as a regular distributed arithmetic array. The simulated gain in speed for the presented multiplier is about 100%. For verification, the multiplier is fabricated in a three metal-layer 0.5µ CMOS process using a standard cell library. The fabricated multiplier chip has been functionally verified.
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| 9. |
- Berkeman, Anders, et al.
(författare)
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A low logic depth complex multiplier using distributed arithmetic
- 2000
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Ingår i: IEEE Journal of Solid-State Circuits. - : Institute of Electrical and Electronics Engineers (IEEE). - 0018-9200 .- 1558-173X. ; 35:4, s. 656-659
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Tidskriftsartikel (refereegranskat)abstract
- A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor. The performance in terms of throughput of the processor is limited by the multiplication. Therefore, the multiplier is optimized to make the input-to-output delay as short as possible. A new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. The multiplier has been fabricated using standard cells in a 0.5-μm process and verified for functionality, speed, and power consumption. Running at 40 MHz, a multiplier with input wordlengths of 16+16 times 10+10 bits consumes 54% less power compared to an distributed arithmetic array multiplier fabricated under equal conditions
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| 10. |
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