| 51. |
- Kanth, R. K., et al.
(författare)
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Study on sustainability and life cycle assessment of RFID antenna
- 2015
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Ingår i: Environmental Engineering and Computer Application - Proceedings of the International Conference on Environmental Engineering and Computer Application, ICEECA 2014. - : CRC Press/Balkema. - 9781138028074 ; , s. 369-372
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Konferensbidrag (refereegranskat)abstract
- This work gives a unique insight into evaluating sustainability, life cycle assessment and environmental emissions of the specified RFID tag antenna that validates the potential for ultra-low cost mass production for green electronics. We have designed a printed RFID antenna that employs commercially available paper substrates, and has capability to endure itself at varying environmental effects. The geometry and dimension of the antenna has been set as per requirement of read range of RFID tag. The environmental emissions profiles global warming, acidification potential, ozone layer depletion and human toxicity potentials are illustrated in this paper.
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| 52. |
- Ling, Li, et al.
(författare)
-
Precisely Controlled Hydration Water for Performance Improvement of Organic-Inorganic Perovskite Solar Cells
- 2016
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Ingår i: Advanced Functional Materials. - : Wiley-VCH Verlagsgesellschaft. - 1616-301X .- 1616-3028. ; 26:28, s. 5028-5034
-
Tidskriftsartikel (refereegranskat)abstract
- Recently, intensive studies on the role of water molecule in the formation of organic-inorganic perovskite film have been reported. However, not only the contradictive phenomena but also the complex processing technique has hindered the widespread use of water molecule in perovskite preparation. Here the hydration water is introduced into the precursors instead of water. By precisely controlling the content of hydration water, a smoother and more uniform perovskite film is obtained through a simple one-step spin coating method. The improvement of perovskite film quality leads to highly efficient planar perovskite solar cells. Summing up the device studies and the investigation of morphology, crystallization, and optical properties, the impact of water molecule in the formation of perovskite crystal and consequences of device performance is understood. Due to its universal adaptability and simplified process, precise control of hydration water is therefore of great utility to high quality perovskite films fabrication and large-scale production of this upcoming photovoltaic technology.
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| 53. |
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| 54. |
- Liu, Lizheng, et al.
(författare)
-
A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
- 2018
-
Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 26:10, s. 2143-2154
-
Tidskriftsartikel (refereegranskat)abstract
- The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.
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| 55. |
- Liu, Lizheng, et al.
(författare)
-
A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network
- 2020
-
Ingår i: 2020 IEEE Nordic Circuits and Systems Conference, NORCAS 2020 - Proceedings. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- The Bayesian Confidence Propagation Neural Network (BCPNN) has been applied in higher level of cognitive intelligence (e.g. working memory, associative memory). However, in the spike-based version of this learning rule the pre-, postsynaptic and coincident activity is traced in three low-passfiltering stages, the calculation processes of weight update are very computationally intensive. In this paper, a hardware architecture of the updating process for lazy update mode is proposed for updating 8 local synaptic state variables. The parallelism by decomposing the calculation steps of formulas based on the inherent data dependencies is optimized. The FPGA-based hardware accelerator of BCPNN is designed and implemented. The experimental results show the updating process on FPGA can be accomplished within 110 ns with a clock frequency of 200 MHz, the updating speed is greatly enhanced compared with the CPU test. The trade-off between performance, accuracy and resources on dedicated hardware is evaluated, and the impact of the module reuse on resource consumption and computing performance is evaluated.
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| 56. |
- Liu, Lizheng, et al.
(författare)
-
An Autonomous Error-Tolerant Architecture Featuring Self-reparation for Convolutional Neural Networks
- 2020
-
Ingår i: Proceeding of the IEEE Vehicular Technology Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Convolutional neural networks are widely used in artificial intelligence and Internet of Things area. As the scale of convolutional neural network expands, more and more processing units are provided for it. The systems are easy prone to error, and any computing problems in any layer of the network will lead to wrong output results. Traditional multimode redundancy methods make the systems more complex, and increase power consumption. This paper proposes an autonomous error-tolerant architecture for convolutional neural networks. Taking the LeNet-5 as an example, the network layers of CNN are mapped on the AET architecture, an error-tolerant synapse is designed to discover the errors, an active evolution scheme is designed to handle unrecoverable errors and implement network reconfiguration. This design is implemented on FPGA, and the experimental results show that this architecture can realize effective error tolerance for convolutional neural network and has fast error recovery ability under the premise of ensuring the same recognition accuracy.
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| 57. |
- Lu, H., et al.
(författare)
-
An optical dynamic study of MAPbBr3 single crystals passivated with MAPbCl3/I3-MAPbBr3 heterojunctions
- 2017
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Ingår i: Physical Chemistry, Chemical Physics - PCCP. - : Royal Society of Chemistry. - 1463-9076 .- 1463-9084. ; 19:6, s. 4516-4521
-
Tidskriftsartikel (refereegranskat)abstract
- Recently, perovskite based solar cells have attracted lots of research interest, some of which is in the passivation of perovskite surfaces, particularly the heterojunction based surface passivation. In this study, the optical dynamics of MAPbBr3 single crystals with and without heterojunction passivation were studied systematically by means of a time-resolved spectroscopic technique for the first time. The emission lifetime of MAPbBr3 single crystals under two-photon (1064 nm) excitation is a few orders of magnitude longer than that measured under one-photon (355 nm or 532 nm) excitation. Interestingly, with surface passivation, the lifetime measured at 355 nm excitations could be tuned significantly, whereas the lifetime change under 1064 nm excitations was considerably less. Our results give a direct evidence of surface quench by comparing the lifetimes before and after surface passivation. Furthermore, the results demonstrate that proper MAPbCl3-MAPbBr3 heterojunctions can dramatically reduce the recombination channels in the surface region, which can be potentially useful for perovskite based solar cells, light emitting diodes (LED), and sensitive detectors.
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| 58. |
- Ma, Ning, et al.
(författare)
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A 101.4 GOPS/W Reconfigurable and Scalable Control-centric Embedded Processor for Domain-specific Applications
- 2016
-
Ingår i: Proceedings - IEEE International Symposium on Circuits and Systems. - : IEEE. - 9781479953400 ; , s. 1746-1749
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Konferensbidrag (refereegranskat)abstract
- Increasing the energy efficiency and performance while providing the customizability and scalability is vital for embedded processors adapting to domain-specific applications such as Internet of Things. In this paper, we proposed a reconfigurable and scalable control-centric architecture, and implemented the design consisting of two cores and an on-chip multi-mode router in 65 nm technology. The reconfigurability is enabled by the restructurable sequence mapping table (SMT) thus the reorganizable functional units. Owing to the integration of the multi-mode router, on-chip or inter-chip network for multi-/many-core computing can be composed for performance extension on demand even in the post-fabrication stage. Control-centric design simplifies the control logic, shrinks the non-functional units and orchestrates the operations to increase the hard are utilization and reduce the excessive data movement for high energy efficiency. As a result, the processor can both conduct general-purpose processing with 29% smaller code size and application-specific processing with over 10 times performance improvement when implementing AES by SMT. The dual-core processor consumes 19.7 μW/MHz with die size of 3.5 mm2. The achieved energy efficiency is 101.4GOPS/W.
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| 59. |
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| 60. |
- Ma, Ning, et al.
(författare)
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A 5Mgate/414mW Networked Media SoC in 0.13um CMOS with 720p Multi-Standard Video Decoding
- 2009
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Ingår i: 2009 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC). - : IEEE Solid-State Circuits Society. - 9781424444342 ; , s. 385-388
-
Konferensbidrag (refereegranskat)abstract
- A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet network interface and coarse-grained configurable video decoding unit. Real-time 1280x720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with core size of 6.4mm * 6.4mm. To achieve low power design, flexible power management strategy is implemented for dynamically control of computational capabilities with various workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280x720@25fps) video streams are decoded. When the SoC decodes real-time CIF (352x288@25fps) video streams, it requires 27MHz system frequency and consumes 95mW.
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