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Sökning: LAR1:kth > Östling Mikael

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1.
  • A. M. Naiini, Maziar, 1980- (författare)
  • Horizontal Slot Waveguides for Silicon Photonics Back-End Integration
  • 2014
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
    • This thesis presents the development of integrated silicon photonic devices. These devices are compatible with the present and near future CMOS technology. High-khorizontal grating couplers and waveguides are proposed. This work consists of simulations and device design, as well as the layout for the fabrication process, device fabrication, process development, characterization instrument development and electro-optical characterizations.The work demonstrates an alternative solution to costly silicon-on-insulator photonics. The proposed solution uses bulk silicon wafers and thin film deposited waveguides. Back-end deposited horizontal slot grating couplers and waveguides are realized by multi-layers of amorphous silicon and high-k materials.The achievements of this work include: A theoretical study of fully etched slot grating couplers with Al2O3, HfO2 and AIN, an optical study of the high-k films with spectroscopic ellipsometry, an experimental demonstration of fully etched SiO2 single slot grating couplers and double slot Al2O3 grating couplers, a practical demonstration of horizontal double slot high-k waveguides, partially etched Al2O3 single slot grating couplers, a study of a scheme for integration of the double slot Al2O3  waveguides with selectively grown germanium PIN photodetectors, realization of test chips for the integrated germanium photodetectors, and study of integration with graphene photodetectors through embedding the graphene into a high-k slot layer.From an application point of view, these high-k slot waveguides add more functionality to the current silicon photonics. The presented devices can be used for low cost photonics applications. Also alternative optical materials can be used in the context of this photonics platform.With the robust design, the grating couplers result in improved yield and a more cost effective solution is realized for integration of the waveguides with the germanium and graphene photodetectors.    
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2.
  • Abedin, Ahmad, et al. (författare)
  • Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density
  • 2016
  • Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-5862 .- 1938-6737. - 9781607685395 ; , s. 615-621
  • Konferensbidrag (refereegranskat)abstract
    • Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.
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3.
  • Abedin, Ahmad, 1984- (författare)
  • Germanium layer transfer and device fabrication for monolithic 3D integration
  • 2021
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
    • Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability
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4.
  • Abedin, Ahmad, et al. (författare)
  • Germanium on Insulator Fabrication for Monolithic 3-D Integration
  • 2018
  • Ingår i: IEEE Journal of the Electron Devices Society. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 2168-6734. ; 6:1, s. 588-593
  • Tidskriftsartikel (refereegranskat)abstract
    • A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.
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5.
  • Abedin, Ahmad, et al. (författare)
  • GeSnSi CVD Epitaxy using Silane, Germane, Digermane, and Tin tetrachloride
  • Tidskriftsartikel (refereegranskat)abstract
    • In this study, strain relaxed and compressive strained Ge1-x-ySnxSiy (0.015≤x≤0.15 and 0≤y≤0.15) layers were epitaxially grown on Si substrate in a chemical vapor deposition reactor at atmospheric pressure. Digermane (Ge2H6) and germane (GeH4) were used as Ge precursors and tin tetrachloride (SnCl4) was used as Sn precursor. The growth temperature was kept below 400ᵒC to suppress Sn out diffusion. The layers crystal quality and strain were characterized using XRD, high resolution reciprocal lattice mapping and transmission electron microscopy and the surface morphology was investigated by atomic force microscopy (AFM). Furthermore, the low temperature epitaxial growth up to 15% Si atoms incorporation in Ge0.94Sn0.06 was demonstrated by adding silane (SiH4) as Si precursor. Sn contents calculated from high resolution XRD patterns were confirmed by Rutherford backscattering spectroscopy which shows that Sn atoms are mostly positioned in substitutional sites. AFM analysis showed below 1nm surface roughness for both strained and strain relaxed GeSn layers which make the promising materials for photonics and electronics applications.
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6.
  • Abedin, Ahmad, et al. (författare)
  • GOI fabrication for monolithic 3D integration
  • 2018
  • Ingår i: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781538637654 ; , s. 1-3
  • Konferensbidrag (refereegranskat)abstract
    • A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.
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7.
  • Abedin, Ahmad, et al. (författare)
  • Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabrication
  • Annan publikation (övrigt vetenskapligt/konstnärligt)abstract
    • In this study, the application of epitaxially grown SixGe1-x films as etch stop layers in a germanium-on-insulator substrate fabrication flow is investigated. Layers with Ge contents from 15% to 70% were epitaxially grown on Si (1 0 0) using silane and germane. It was found that the Ge content in the films is independent of the growth temperature for fixed partial pressure ratios. At low growth temperatures the activation energy is found to be 1.8 eV which points to a hydrogen desorption limited growth rate mechanism. At growth temperatures of less than 500℃, the surface roughness is <1 nm. This surface roughness does not change when the films are grown on Ge substrates. Finally, a fully strained Si0.5Ge0.5 film was grown on Ge strain relaxed buffer at 450℃. This layer demonstrates etch selectivity of >400:1 towards Ge in diluted SC-1. This result enables the integration of the Si0.5Ge0.5 film as an etch stop layer for single crystalline germanium-on-insulator substrate fabrication.
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8.
  • Abedin, Ahmad, et al. (författare)
  • Sensitivity of the crystal quality of SiGe layers grown at low temperatures by trisilane and germane
  • 2016
  • Ingår i: Thin Solid Films. - : Elsevier. - 0040-6090 .- 1879-2731. ; 613, s. 38-42
  • Tidskriftsartikel (refereegranskat)abstract
    • This work investigates the crystal quality of SiGe layers grown at low temperatures using trisilane, and germane precursors. The crystal quality sensitivity was monitored for hydrogen chloride and/or minor oxygen amount during SiGe epitaxy or at the interface of SiGe/Si layers. The quality of the epi-layerswas examined by quantifying noise parameter, K-1/f obtained from the power spectral density vs. 1/f curves. The results indicate that while it is difficult to detect small defect densities in SiGe layers by physical material characterization, the noise measurement could reveal the effects of oxygen contamination as low as 0.16mPa inside and in the interface of the layers.
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9.
  • Asadollahi, Ali, 1980- (författare)
  • Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration
  • 2018
  • Doktorsavhandling (övrigt vetenskapligt/konstnärligt)abstract
    • The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.  The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.
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10.
  • Asadollahi, Ali, et al. (författare)
  • Fabrication of relaxed germanium on insulator via room temperature wafer bonding
  • 2014
  • Ingår i: ECS Transactions. - : Electrochemical Society. - 1938-6737. ; , s. 533-541
  • Konferensbidrag (refereegranskat)abstract
    • We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.
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