| 1. |
- Ahmad, S. A., et al.
(författare)
-
Penta-band antenna with defected ground structure for wireless communication applications
- 2019
-
Ingår i: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019. - : Institute of Electrical and Electronics Engineers Inc.. - 9781538695098
-
Konferensbidrag (refereegranskat)abstract
- This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.
|
|
| 2. |
- Ahmad, Waqar, et al.
(författare)
-
Decoupling capacitance for the power integrity of 3D-DRAM-over-logic system
- 2012
-
Ingår i: IEEE 13th Electronics Packaging Technology Conference (EPTC), 2011. - : IEEE conference proceedings. - 9781457719813 ; , s. 590-594
-
Konferensbidrag (refereegranskat)abstract
- The 3D-DRAM stacked over the processor is a vibrant technique in order to overcome the memory wall as well as the bandwidth wall problems. We considered a system with two DRAM dies over a single processor die. We assumed the decoupling capacitors to be placed on each DRAM die and connected to the power distribution TSV pairs, where the TSVs pass through the DRAM stack. In this paper we proposed a mathematical model for the optimum value of the decoupling capacitance on each DRAM die along with the optimum values of the effective resistance of the interconnecting power distribution TSV pairs in order to ensure the power integrity of the logic load during switching. The proposed model has a maximum of 1.1% error as compared to the Ansoft Nexxim4.1.
|
|
| 3. |
- Ahmad, Waqar, et al.
(författare)
-
Fast Transient Simulation Algorithm for a 3D Power distribution Bus
- 2010
-
Ingår i: Proceedings of IEEE Asia Symposium on Quality Electronic Design. ; , s. 343-350
-
Konferensbidrag (refereegranskat)abstract
- Extensive transient simulations for on-chip power delivery networks are required to analyze power delivery fluctuations caused by dynamic IR and Ldi/dt drops. Speed and memory has become a bottleneck for simulation of power distribution networks in modern VLSI design where clock frequency is of the order of GHz. The traditional SPICE based tools are very slow and consume a lot of memory during simulation. The problem is further aggravated for huge networks like power distribution network within a stack of ICs inter-connected through TSVs. This type of 3D power distribution network may contain billions of nodes at a time. In this paper we proposed a faster transient simulation algorithm using visual C++. First we reduce 3D power distribution bus containing n nodes to a two terminal 7 network. Then we solve this two terminal reduced network for voltages and currents. After this, we apply back solving algorithm to the network to solve it for each of the intermediate nodes using visual C++. The proposed algorithm is quite accurate with 1-2% error when compared with Ansoft Nexxim4.1. The proposed algorithm is several times faster than Ansoft Nexxim as well as consumes significantly less memory as compared to Nexxim.
|
|
| 4. |
- Ahmad, Waqar, et al.
(författare)
-
Modeling of peak-to-peak switching noise along a vertical chain of power distribution TSV pairs in a 3D stack of ICs interconnected through TSVs
- 2010
-
Ingår i: 28th Norchip Conference, NORCHIP 2010.
-
Konferensbidrag (refereegranskat)abstract
- On-chip power supply noise has become a bottleneck in 3D ICs as scaling of the supply network impedance has not been kept up with increasing device densities and operating currents with each technology node due to limited wire resources. In this paper we proposed an efficient and accurate model to estimate peak-to-peak switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of ICs. The proposed model is quite accurate with only 2-3% difference from Ansoft Nexxim4.1 equivalent model. The proposed model is 3-4 times faster than Nexxim4.1 as well as consumes two times less memory as compared to Nexxim4.1equivalent model. We analyzed peak-to-peak switching noise along a vertical chain of power distribution TSV pairs by varying physical dimensions of TSVs and value of decoupling capacitance. We also thoroughly investigated the peak-to-peak noise sensitivity to TSV effective inductance and decoupling capacitance.
|
|
| 5. |
- Ahmad, Waqar, et al.
(författare)
-
Peak-to-peak Switching Noise and LC Resonance on a Power Distribution TSV Pair
- 2010
-
Ingår i: 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010. - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 173-176
-
Konferensbidrag (refereegranskat)abstract
- How peak-to-peak switching noise as well as the LC resonance term varies by varying different circuit parameters of a power distribution TSV pair (having decoupling capacitance and logic load), within a 3D stack of ICs interconnected through TSVs.
|
|
| 6. |
- Ahmad, Waqar, et al.
(författare)
-
Power distribution TSVs induced core switching noise
- 2011
-
Ingår i: Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2010 IEEE. - : IEEE conference proceedings. - 9781424490691
-
Konferensbidrag (refereegranskat)abstract
- Size of on-chip interconnects as well as the supply voltage is reducing with each technology node whereas the operating speed is increasing in modern VLSI design. Today, the package inductance and resistance has been reduced to such an extent that core switching noise caused by on-chip inductance and on-chip resistance is gaining importance as compared to I/O drivers switching noise. Both on-chip inductance and skin effect are prime players at frequencies of the order of GHz. The problem is further aggravated when chips are interconnected through TSVs to form a 3D integrated stack in order to achieve low form factor and high integration density. In this paper we analysed peak core switching noise in a 3D stack of integrated chips interconnected through power distribution TSV pairs, through our comprehensive mathematical model which has been proved to be quite accurate as compared to SPICE. We analysed the effect of number of chips in a 3D stack, rise time, decoupling capacitance, and skin effect on power distribution TSVs induced core switching noise in this paper.
|
|
| 7. |
- Ahmad, Waqar, et al.
(författare)
-
Power Integrity Optimization of 3D Chips Stacked Through TSVs
- 2009
-
Ingår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS. - NEW YORK : IEEE. - 9781424444489 ; , s. 105-108
-
Konferensbidrag (refereegranskat)abstract
- On-chip power distribution network model for simultaneous switching of 3D ICs stacked through TSVs to choose TSV pattern, maximum number of chips in a stack and location of the decoupling capacitor for early design trade-offs.
|
|
| 8. |
- Albrecht, Steffen, et al.
(författare)
-
A Frequency Synthesizer Architecture Using Frequency Difference Detection
- 2003
-
Konferensbidrag (refereegranskat)abstract
- In this paper, we present a frequency synthesizer architecture and its simulation results. Frequency differences are detected digitally with a high speed counter. The oscillator output frequency is used as a clock signal for the digital blocks, whereas the output frequency accuracy can be traded off with the synthesizer settling time.
|
|
| 9. |
- Ali, Mai, et al.
(författare)
-
Autonomous Patient/Home Health Monitoring powered by Energy Harvesting
- 2017
-
Ingår i: Globecom 2017 - 2017 IEEE Global Communications Conference. - : Institute of Electrical and Electronics Engineers (IEEE). - 9781509050192
-
Konferensbidrag (refereegranskat)abstract
- This paper presents the design of an autonomous smart patient/home health monitoring system. Both patient physiological parameters as well as room conditions are being monitored continuously to insure patient safety. The sensors are connected on an IoT regime, where the collected data is wirelessly transferred to a nearby gateway which performs preliminary data analysis, commonly referred to as fog computing, to make sure emergency personnel and healthcare providers are notified in case patient being monitored is at risk. To achieve power autonomy three energy harvesting sources are proposed, namely, solar, RF and thermal. The design of the RF energy harvesting system is demonstrated, where novel multiband antenna is fabricated as well as an efficient RF-DC rectifier achieving maximum conversion efficiency of 84%. Finally, the sensor node is tested with different type of sensors and settings while being solely powered by a Photovoltaic (PV) solar cell.
|
|
| 10. |
|
|
