| 1. |
- Anderson, John B, et al.
(författare)
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Faster-Than-Nyquist Signaling
- 2013
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Ingår i: Proceedings of the IEEE. - 0018-9219. ; 101:8, s. 1817-1830
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we survey Faster-than-Nyquist (FTN) signaling, an extension of ordinary linear modulation in which the usual data bearing pulses are simply sent faster, and consequently are no longer orthogonal. Far from a disadvantage, this innovation can transmit up to twice the bits as ordinary modulation at the same bit energy, spectrum, and error rate. The method is directly applicable to orthogonal frequency division multiplex (OFDM) and quadrature amplitude modulation (QAM) signaling. Performance results for a number of practical systems are presented. FTN signaling raises a number of basic issues in communication theory and practice. The Shannon capacity of the signals is considerably higher.
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| 2. |
- Dasalukunte, Deepak, et al.
(författare)
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A Transmitter Architecture for Faster-than-Nyquist Signaling Systems
- 2009
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Ingår i: Proceedings, IEEE International Symposium on Circuits and Systems, 2009. - 9781424438273 ; , s. 1028-1031
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Konferensbidrag (refereegranskat)abstract
- This paper presents the complexity analysis of a transmitter architecture for a faster-than-Nyquist (FTN) system. Complexity issues in terms of computations and memory requirements to achieve an FTN system are dealt with. An OFDM based multi-carrier system is considered as it is one of the most widely used in upcoming wireless standards. Retaining the modules within the OFDM transmitter helps in exploiting the already optimized and hardware efficient structures, the IFFT being one. From an implementation perspective the introduction of FTN introduces negligible overhead for the transmitter.
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| 3. |
- Dasalukunte, Deepak, et al.
(författare)
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Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier systems
- 2011
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Ingår i: [Host publication title missing]. - 2159-3477. ; , s. 359-360
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Konferensbidrag (refereegranskat)abstract
- Abstract in UndeterminedFaster-than-Nyquist (FTN) signaling is a method of improving bandwidth efficiency by transmitting information beyond Nyquist's orthogonality limit for interference free transmission. Previously have theoretically established that FTN can provide improved bandwidth efficiency. However, this comes at the cost of higher decoding complexity at the receiver. Our work has evaluated multicarrier FTN signaling for its implementation feasibility and complexity overhead compared to the gains in bandwidth efficiency. The work carried out in this research project includes a systems perspective evaluating performance, algorithm hardware tradeoffs and a hardware architecture leading to a silicon implementation of the decoder for FTN signaling. From the systems perspective, co-existence of FTN and OFDM based multicarrier system has been evaluated. OFDM being a part of many existing and upcoming broadband access technologies such as WLAN, LTE, DVB, this analogy is motivated. On the hardware aspect, the proposed architecture can accommodate both OFDM and FTN systems. The processing blocks in transmitter and receiver were designed for reuse and carry out different functions in the transceiver. Furthemore, the hardware could be configured to operate at varying bandwidth efficiencies (by FTN signaling) to exploit the channel conditions. The decoder implementation also considered block sizes and data rates to comply with the 3GPP standard. The decoding is carried out in as few as 8 iterations making it more practical for implementation in power constrained mobile devices. The decoder is implemented in 65nm CMOS process and occupies a total chip area of 0.8mm2.
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| 4. |
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| 5. |
- Kamuf, Matthias, et al.
(författare)
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A hardware efficiency analysis for simplified trellis decoding blocks
- 2005
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Ingår i: [Host publication title missing]. - 1520-6130. - 0780393333 ; 2005, s. 128-132
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Konferensbidrag (refereegranskat)abstract
- Two simplifications for trellis decoding blocks are analyzed in terms of hardware efficiency. Both architectures use a complementary property of the best rate 1/n convolutional codes to reduce arithmetic complexity. While the reduction can be calculated straightforward in the first approach (17%), the other approach relies on modified computational operations and hence this reduction is not as evident. It is shown that for rate 1/2 codes the first approach is preferable for hardware implementation in terms of area and speed.
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| 6. |
- Kamuf, Matthias, et al.
(författare)
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A simplified computational kernel for trellis-based decoding
- 2004
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Ingår i: IEEE Communications Letters. - 1089-7798. ; 8:3, s. 156-158
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Tidskriftsartikel (refereegranskat)abstract
- A simplified branch metric and add-compare-select (ACS) unit is presented for use in trellis-based decoding architectures. The simplification is based on a complementary property of best feedforward and some systematic feedback encoders. As a result, one adder is saved in every other ACS unit. Furthermore, only half the branch metrics have to be calculated. It is shown that this simplification becomes especially beneficial for rate 1/2 convolutional codes. Consequently, area and power consumption will be reduced in a hardware implementation.
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| 7. |
- Kamuf, Matthias, et al.
(författare)
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A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
- 2008
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Ingår i: Proceedings, Norchip Conference. ; , s. 137-141
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Konferensbidrag (refereegranskat)abstract
- This paper discusses design and measurements of a flexible Viterbi decoder fabricated in 130-nm digital CMOS. Flexibility was incorporated by providing various code rates and modulation schemes to adjust to varying channel conditions. Based on previous trade-off studies, flexible building blocks were carefully designed to cause as little area penalty as possible. The chip runs down to a minimal core supply of 0.8V. It turns out that striving for more modulation schemes is beneficial in terms of power consumption once the price is paid for accepting different code rates viz. radices in the trellis and survivor path units.
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| 8. |
- Kamuf, Matthias, et al.
(författare)
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Architectural considerations for rate-flexible trellis processing blocks
- 2005
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Ingår i: 2005 IEEE 16th International Symposium on Personal, Indoor and Mobile Radio Communications. - 9783800729098 ; , s. 1076-1080
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Konferensbidrag (refereegranskat)abstract
- A flexible channel decoding platform should be able to operate in varying communication scenarios, and different code rates have to be supported. Therefore, we present a framework that allows efficient processing of rate-flexible trellises. Using a fundamental computational unit for trellis-based decoding, formal principles are obtained to emulate more complex trellises. In a design example, such a computational block supports both rate 1/c convolutional codes and set partition codes with subset selectors of rate 2/3. Synthesis results show the hardware requirements for two different architectural approaches
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| 9. |
- Kamuf, Matthias, et al.
(författare)
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Area and power efficient trellis computational blocks in 0.13μm CMOS
- 2005
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Ingår i: IEEE International Symposium on Circuits and Systems (ISCAS). - 0780388348 ; , s. 344-347
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Konferensbidrag (refereegranskat)abstract
- Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13μm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption
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| 10. |
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