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| 2. |
- Samuelson, Lars, et al.
(författare)
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Semiconductor nanowires for 0D and 1D physics and applications
- 2004
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Ingår i: Physica E: Low-Dimensional Systems and Nanostructures. - : Elsevier BV. - 1386-9477. ; 25:2-3, s. 313-318
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Tidskriftsartikel (refereegranskat)abstract
- During the last 5 years the potential for applications of semiconductor nanowires has grown rapidly via the development of methods for catalytically induced nanowire growth using the, so-called vapor-liquid-solid (VLS) growth mode. The VLS method offers a high degree of control of parameters such as position, diameter, length and composition, including the realization of atomically abrupt heterostructure interfaces inside a nanowire. In this review, we summarize the progress and the standing of our research from the point of view of controlled growth, structural and electronic properties and in terms of different families of devices which have been possible to realize. (C) 2004 Elsevier B.V. All rights reserved.
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| 3. |
- Tizno, Ofogh, et al.
(författare)
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Radial tunnel diodes based on InP/InGaAs core-shell nanowires
- 2017
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 110:11
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Tidskriftsartikel (refereegranskat)abstract
- We report on the fabrication and characterization of radial tunnel diodes based on InP(n+)/InGaAs(p+) core-shell nanowires, where the effect of Zn-dopant precursor flow on the electrical properties of the devices is evaluated. Selective and local etching of the InGaAs shell is employed to access the nanowire core in the contact process. Devices with an n+-p doping profile show normal diode rectification, whereas n+-p+ junctions exhibit typical tunnel diode characteristics with peak-to-valley current ratios up to 14 at room temperature and 100 at 4.2 K. A maximum peak current density of 28 A/cm2 and a reverse current density of 7.3 kA/cm2 at VSD = −0.5 V are extracted at room temperature after normalization with the effective junction area.
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| 4. |
- Dey, Anil, et al.
(författare)
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15 nm diameter InAs nanowire MOSFETs
- 2011
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Ingår i: [Host publication title missing]. - 1548-3770. ; , s. 21-22
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Konferensbidrag (refereegranskat)abstract
- InAs is an attractive channel material for III–V nanowire MOSFETs and early prototype high performance nanowire transistors have been demonstrated1. As the gate length is reduced, the nanowire diameter must be scaled quite aggressively in order to suppress short-channel effects2. However, a reduction in transconductance (gm) and drive current (ION) could be expected due to increased surface scattering for thin wires. We present data for the device properties of thin InAs nanowires, with diameters in the 15 nm range, and investigate possible improvements of the performance focusing on transistor applications. In order to boost ION, the source and drain resistance need to be reduced. Several doping sources were therefore evaluated in the study, among them selenium (Se), tin (Sn) and sulphur (S) to form n-i-n structures. We report very high current densities, up to 33 MA/cm2, comparable to modern HEMTs3, and a normalized transconductance of 1.8 S/mm for a nanowire with an intrinsic segment of nominally 150 nm and a diameter of 15 nm.
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| 5. |
- Dey, Anil, et al.
(författare)
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High-performance 15 nm diameter InAs nanowire Ω-gate MOSFETs
- 2012
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Konferensbidrag (refereegranskat)abstract
- In this paper we present 15 nm InAs nanowire lateral MOSFETs with an Ω-gate. The nanowires are grown from size-selected Au-aerosols by means of metal-organic vapor phase epixtaxy (MOVPE). In order to reduce the source and drain resistances, n-type dopants were introduced in the bottom and top parts of the nanowire forming a n-i-n structure. We report experimental data for 15 nm InAs nanowire MOSFETs, LG = 150 nm, with a normalized transconducatance gm = 0.7 S/mm (normalized to the circumference) and a current density Je = 24 MA/cm, comparable to modern high electron mobility transistors (HEMTs)
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| 6. |
- Dey, Anil, et al.
(författare)
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High-Performance InAs Nanowire MOSFETs
- 2012
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 33:6, s. 791-793
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, we present a 15-nm-diameter InAs nanowire MOSFET with excellent on and off characteristics. An n-i-n doping profile was used to reduce the source and drain resistances, and an Al2O3/HfO2 bilayer was introduced in the high-k process. The nanowires exhibit high drive currents, up to 1.25 A/mm, normalized to the nanowire circumference, and current densities up to 34 MA/cm2 (VD = 0.5 V). For a nominal LG = 100 nm, we observe an extrinsic transconductance (gm) of 1.23 S/mm and a subthreshold swing of 93 mV/decade at VD = 10 mV.
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| 7. |
- Ganjipour, Bahram, et al.
(författare)
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Tunnel Field-Effect Transistors Based on InP-GaAs Heterostructure Nanowires.
- 2012
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Ingår i: ACS Nano. - : American Chemical Society (ACS). - 1936-086X .- 1936-0851. ; 6:4, s. 3109-3113
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Tidskriftsartikel (refereegranskat)abstract
- We present tunneling field-effect transistors fabricated from InP-GaAs heterostructure nanowires with an n-i-p doping profile, where the intrinsic InP region is modulated by a top gate. The devices show an inverse subthreshold slope down to 50 mV/dec averaged over two decades with an on/off current ratio of approximately 10(7) for a gate voltage swing (V(GS)) of 1 V and an on-current of 2.2 μA/μm. Low-temperature measurements suggest a mechanism of trap-assisted tunneling, possibly explained by a narrow band gap segment of InGaAsP.
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| 8. |
- Muench, S., et al.
(författare)
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Time-resolved photoluminescence investigations on HfO2-capped InP nanowires
- 2010
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 21:10
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Tidskriftsartikel (refereegranskat)abstract
- We have employed time-resolved photoluminescence (PL) spectroscopy to study the impact of HfO2 surface capping by atomic layer deposition (ALD) on the optical properties of InP nanowires (NWs). The deposition of high-kappa dielectrics acting as a gate oxide is of particular interest in view of possible applications of semiconductor NWs in future wrap-gated field effect transistors (FETs). A high number of charged states at the NW-dielectrics interface can strongly degrade the performance of the FET which explains the strong interest in high quality deposition of high-kappa dielectrics. In the present work we show that time-resolved spectroscopy is a valuable and direct tool to monitor the surface quality of HfO2-capped InP NWs. In particular, we have studied the impact of ALD process parameters as well as surface treatment prior to the oxide capping on the NW-dielectrics interface quality. The best results in terms of the surface recombination velocity (S-0 = 9.5 x 10(3) cm s(-1)) were obtained for InP/GaP core/shell NWs in combination with a low temperature (100 degrees C) ALD process. While the present report focuses on the InP material system, our method of addressing the surface treatment for semiconductors with high-kappa dielectrics will also be applicable to nanoelectronic devices based on other III/V material systems such as InAs.
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| 9. |
- Storm, Kristian, et al.
(författare)
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Dual-gate induced InP nanowire diode
- 2011
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Ingår i: Physics of Semiconductors: 30th International Conference on the Physics of Semiconductors. - : AIP. - 1551-7616 .- 0094-243X. ; 1399, s. 279-280
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Konferensbidrag (refereegranskat)abstract
- Semiconductor devices are heavily dependent on dopant incorporation in order to control the electrical properties. In this paper we investigate the possibility of using gates wrapped around a nanowire (NW) channel as a way of tuning the Fermi level position, in certain cases removing the need for dopants and providing a more dynamical way of setting the device properties. InP NW devices with omega gates are fabricated, and a p-n junction is formed in a nominally intrinsic NW channel. In order to further increase the electrostatic control of the channel and other device properties, vertical devices are discussed as a promising way of implementing this type of device.
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| 10. |
- Storm, Kristian, et al.
(författare)
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Gate-Induced Fermi Level Tuning in InP Nanowires at Efficiency Close to the Thermal Limit.
- 2011
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Ingår i: Nano Letters. - : American Chemical Society (ACS). - 1530-6992 .- 1530-6984. ; 11, s. 1127-1130
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Tidskriftsartikel (refereegranskat)abstract
- As downscaling of semiconductor devices continues, one or a few randomly placed dopants may dominate the characteristics. Furthermore, due to the large surface-to-volume ratio of one-dimensional devices, the position of the Fermi level is often determined primarily by surface pinning, regardless of doping level. In this work, we investigate the possibility of tuning the Fermi level dynamically with wrap-around gates, instead of statically setting it using the impurity concentration. This is done using Ω-gated metal-oxide-semiconductor field-effect transistors with HfO(2)-capped InP nanowires as channel material. It is found that induced n-type devices exhibit an optimal inverse subthreshold slope of 68 mV/decade. By adjusting the growth and process parameters, it is possible to produce ambipolar devices, in which the Fermi level can be tuned across the entire band gap, making it possible to induce both n-type and p-type conduction.
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