| 1. |
- Ayatolahi, Fatemeh, 1984, et al.
(författare)
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A study of the impact of single bit-flip and double bit-flip errors on program execution
- 2013
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Ingår i: Lect. Notes Comput. Sci.. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 9783642407925 ; , s. 265-276
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Konferensbidrag (refereegranskat)abstract
- This paper presents the results of an extensive experimental study of bit-flip errors in instruction set architecture registers and main memory locations. Comprising more than two million fault injection experiments conducted with thirteen benchmark programs, the study provides insights on whether it is necessary to consider double bit-flip errors in dependability benchmarking experiments. The results show that the proportion of silent data corruptions in the program output, is almost the same for single and double bit errors. In addition, we present detailed statistics about the error sensitivity of different target registers and memory locations, including bit positions within registers and memory words. These show that the error sensitivity varies significantly between different bit positions and registers. An important observation is that injections in certain bit positions always have the same impact regardless of when the error is injected.
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| 2. |
- Ayatolahi, Fatemeh, 1984, et al.
(författare)
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Sources of Variation in Error Sensitivity Measurements, Significant or Not?
- 2018
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Ingår i: Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN-W 2018. - 9781538665534 ; , s. 71-72
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Konferensbidrag (refereegranskat)abstract
- Measuring the error sensitivity by fault injection is an important method for assessing the dependability of computer systems. In this paper, we define error sensitivity as the conditional probability that a hardware-related error causes a silent data corruption. When measuring the error sensitivity it is important to consider how the experimental setup and the workload characteristics affect the estimated error sensitivity. We consider five such potential sources of variation (PSVs) in this paper. Three of these are related to the workload: i) input profile, ii) source code implementation, and, iii) use of compiler optimization. Two are related to the experimental setup: i) single vs. double bit-flips, and ii) inject-on-read vs. inject-on-write. The paper discusses the applicability of different statistical tests for assessing whether a PSV has a significant impact on error sensitivity.
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| 3. |
- Di Leo, D., et al.
(författare)
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On the impact of hardware faults - An investigation of the relationship between workload inputs and failure mode distributions
- 2012
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Ingår i: Lect. Notes Comput. Sci.. - Berlin, Heidelberg : Springer Berlin Heidelberg. - 1611-3349 .- 0302-9743. - 9783642336775 ; , s. 198-209
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Konferensbidrag (refereegranskat)abstract
- Technology scaling of integrated circuits is making transistors increasingly sensitive to process variations, wear-out effects and ionizing particles. This may lead to an increasing rate of transient and intermittent errors in future microprocessors. In order to assess the risk such errors pose to safety critical systems, it is essential to investigate how temporary errors in the instruction set architecture (ISA) registers and main memory locations influence the behaviour of executing programs. To this end, we investigate - by means of extensive fault injection experiments - how such errors affect the execution of four target programs. The paper makes three contributions. First, we investigate how the failure modes of the target programs vary for different input sets. Second, we evaluate the error coverage of a software-implemented hardware fault tolerant technique that relies on triple-time redundant execution, majority voting and forward recovery. Third, we propose an approach based on assembly language metrics which can be used to correlate the dynamic fault-free behaviour of a program with its failure mode distribution obtained by fault injection.
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| 4. |
- Folkesson, Peter, 1968, et al.
(författare)
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Back-to-Back Fault Injection Testing in Model-Based Development
- 2015
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Ingår i: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics). - Cham : Springer International Publishing. - 1611-3349 .- 0302-9743. - 9783319242545 - 9783319242552 ; 9337, s. 135-148
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Konferensbidrag (refereegranskat)abstract
- Today, embedded systems across industrial domains (e.g., avionics, automotive) are representatives of software-intensive systems with increasing reliance on software and growing complexity. It has become critically important to verify software in a time, resource and cost effective manner. Furthermore, industrial domains are striving to comply with the requirements of relevant safety standards. This paper proposes a novel workflow along with tool support to evaluate robustness of software in model-based development environment, assuming different abstraction levels of representing software. We then show the effectiveness of our technique, on a brake-by-wire application, by performing back-to-back fault injection testing between two different abstraction levels using MODIFI for the Simulink model and GOOFI-2 for the generated code running on the target microcontroller. Our proposed method and tool support facilitates not only verifying software during early phases of the development lifecycle but also fulfilling back-to-back testing requirements of ISO 26262 when using model-based development.
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| 5. |
- Sangchoolie, Behrooz, et al.
(författare)
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A Comparison of Inject-on-Read and Inject-on-Write in ISA-Level Fault Injection
- 2016
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Ingår i: Proceedings - 2015 11th European Dependable Computing Conference, EDCC 2015. - : Institute of Electrical and Electronics Engineers Inc.. - 9781467392891 ; , s. 178-189, s. 178-189
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Konferensbidrag (refereegranskat)abstract
- ISA-level fault injection, i.e. the injection of bit-flip faults in Instruction Set Architecture (ISA) registers and main memory words, is widely used for studying the impact of transient and intermittent hardware faults in computer systems. This paper compares two techniques for ISA-level fault injection: inject-on-read, and inject-on-write. The first technique injects bit-flips in a data-item (the content of a register or memory word) just before the data-item is read by a machine instruction, while the second one injects bit-flips in a data-item just after it has been updated by a machine instruction. In addition, the paper compares two variants of inject-on-read, one where all faults are given the same weight and one where weight factors are used to reflect the time a data-item spends in a register or memory word. The weighted injected-on-read aims to accurately model soft errors that occur when an ionizing particle perturbs a data-item while it resides in an ISA register or a memory word. This is in contrast to inject-on-write, which emulates errors that propagate into an ISA register or a memory word. Our experiments show significant differences in the results obtained with the three techniques.
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| 6. |
- Sangchoolie, Behrooz, et al.
(författare)
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A study of the impact of bit-flip errors on programs compiled with different optimization levels
- 2014
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Ingår i: Proceedings - 2014 10th European Dependable Computing Conference, EDCC 2014. - : IEEE Computer Society. - 9781479938032 ; , s. 146-157
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Konferensbidrag (refereegranskat)abstract
- In this paper we study the impact of compiler optimizations on the error sensitivity of twelve benchmark programs. We conducted extensive fault injection experiments where bit-flip errors were injected in instruction set architecture registers and main memory locations. The results show that the percentage of silent data corruptions (SDCs) in the output of the optimized programs is only marginally higher compare to that observed for the non-optimized programs. This suggests that compiler optimizations can be used in safety- and mission-critical systems without increasing the risk that the system produces undetected erroneous outputs. In addition, we investigate to what extent the source code implementation of a program affects the error sensitivity of a program. To this end, we perform experiments with five implementations of a bit count algorithm. In this investigation, we consider the impact of the implementation as well as compiler optimizations. The results of these experiments give valuable insights into how compiler optimizations can be used to reduce error sensitive of registers and main memory sections. They also show how sensitive locations requiring additional protection, e.g., by the use of software-based fault tolerance techniques, can be identified.
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| 7. |
- Sangchoolie, Behrooz, et al.
(författare)
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An investigation of the fault sensitivity of four benchmark workloads
- 2012
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Ingår i: Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI). - : Gesellschaft fur Informatik (GI). - 1617-5468. - 9783885796022 ; , s. 468-479
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Konferensbidrag (refereegranskat)abstract
- This paper presents an experimental study of the fault sensitivity of four programs included in the MiBench test suit. We investigate their fault sensitivity with respect to hardware faults that manifest as single bit flips in main memory locations and instruction set architecture registers. To this end, we have conducted extensive fault injection experiments with two versions of each program, one basic version and one where the program is equipped with software-implemented hardware fault tolerance (SIHFT) through triple time redundant execution, majority voting and forward recovery (TTR-FR). The results show that TTR-FR achieves an error coverage between 94.6% and 99.2%, while the non-fault-tolerant versions achieve an error coverage between 55.8% and 81.1%. To gain understanding of the origin of the non-covered faults, we provide statistics on the fault sensitivity of different source code blocks, physical fault locations (instruction set architecture registers and main memory words) and different categories of machine instructions.
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| 8. |
- Sangchoolie, Behrooz, 1986, et al.
(författare)
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Benchmarking the Hardware Error Sensitivity of Machine Instructions
- 2013
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Ingår i: Proceedings of the 2013 IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 9).
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Konferensbidrag (refereegranskat)abstract
- This paper presents the results of an extensive fault injection study of the impact of processor faults that manifest as bit flip errors in instruction set architecture registers and main memory locations. The aim is to investigate if bit errors that propagate to the source registers or memory locations of a given class of machine instructions have a similar probability of generating undetected value failures (i.e., silent data corruptions) for different programs. The results show a fairly large variation in the error sensitivity over different programs for all classes of machine instructions, which indicates that the effectiveness of error mitigation techniques that target specific machine instructions may vary significantly for different programs.
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