| 1. |
- Chen, S., et al.
(författare)
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A solder joint structure with vertically aligned carbon nanofibres as reinforcements
- 2014
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Ingår i: Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014. - 9781479940264 ; , s. Art. no. 6962851-
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Konferensbidrag (refereegranskat)abstract
- In this paper, a solder joint structure was developed for the electronic packaging industry. Vertically aligned carbon nanofibres (VACNFs) were grown, transferred and used at the interface between Si/Au pads and Sn-3.0Ag-0.5Cu (SAC305) alloy as reinforcements in order to increase the solder joint thermal fatigue resistance. The transfer and assembly processes related to VACNFs were optimised and developed. The thermal cycling test results show that the thermal fatigue life of VACNF/SAC305 solder joints is 40% longer than that of pure SAC305. The dye and pry analysis and scanning electron microscopy observation prove that the VACNFs can effectively delay the crack propagation near the interface and consequently prolong the solder joint thermal fatigue life.
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| 2. |
- Chen, Si, 1981, et al.
(författare)
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Sn-3.0Ag-0.5Cu Nanocomposite Solder Reinforced With Bi2Te3 Nanoparticles
- 2015
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Ingår i: IEEE Transactions on Components, Packaging and Manufacturing Technology. - : Institute of Electrical and Electronics Engineers (IEEE). - 2156-3985 .- 2156-3950. ; 5:8, s. 1186-1196
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Tidskriftsartikel (refereegranskat)abstract
- Nanocomposite solders are regarded as one of the most promising interconnect materials for the high-density electronic packaging due to their high mechanical strength and fine microstructure. However, the developments of nanocomposite solders have been limited by the inadequate compatibility between nanoparticles and solder matrix with respect to density, hardness, coefficient of thermal expansion, and surface activity. The compatibility issue will lead to a huge loss of nanoparticles from the solder matrix after the reflow soldering process. The thermal fatigue resistance of solder joint will also become degraded. Therefore, aiming to solve this problem, a novel nanocomposite solder consisting of Bi2Te3 semiconductor nanoparticles and Sn-3.0Ag-0.5Cu (SAC305) solder is presented. The effect of nanoparticles on the viscosity of solder paste and the void content of solder bump was first studied. Then, a series of analysis on the composition and microstructure of the solder bump were completed using transmission electron microscopy, X-ray diffraction, inductively coupled plasma-mass spectrometry, scanning electron microscopy, and energy dispersive X-ray spectroscopy. The survival rate of nanoparticles in the solder bump after reflow soldering process reaches as high as 80%. The refined microstructure was observed from the cross section of the nanocomposite solders. The shear test showed that the average mechanical strength of SAC305 solder after the addition of Bi2Te3 nanoparticles was higher. Meanwhile, no thermal fatigue resistance degradation was detected in the nanocomposite solder after 1000 thermal cycles in the range of -40 degrees C to 115 degrees C.
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| 3. |
- Daon, J., et al.
(författare)
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Chemically enhanced carbon nanotubes based Thermal Interface Materials
- 2015
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Ingår i: THERMINIC 2015 - 21st International Workshop on Thermal Investigations of ICs and Systems 2015. - 9781467397056
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Konferensbidrag (refereegranskat)abstract
- With progress in microelectronics the component density on a device increases drastically. As a consequence the power density reaches levels that challenge device reliability. New heat dissipation strategies are needed to efficiently drain heat. Thermal Interface Materials (TIMs) are usually used to transfer heat across interfaces, for example between a device and its packaging. Vertically Aligned Carbon Nanotubes (VACNTs) can be used to play this role. Indeed, carbon nanotubes are among the best thermal conductors (similar to 3.000 W/mK) and in the form of VACNT mats, show interesting mechanical properties. On one side, VACNTs are in contact with their growth substrate and there is a low thermal resistance. On the other side, good contact must be created between the opposite substrate and the VACNTs in order to decrease the contact thermal resistance. A thin-film deposition of an amorphous material can be used to play this role. This paper reports a chemically enhanced carbon nanotube based TIM with creation of chemical bonds between the polymer and VACNTs. We show that these covalent bonds enhance the thermal transfer from VACNTs to a copper substrate and can dramatically decrease local resistances. Implementation processes and thermal characterizations of TIMs are studied and reported.
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| 4. |
- Daon, J., et al.
(författare)
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Electrically conductive thermal interface materials based on vertically aligned carbon nanotubes mats
- 2014
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Ingår i: IEEE 20th International Workshop on Thermal Investigation of ICs and Systems (Therminic). Greenwich, London, United Kingdom, 24-26 September 2014. - 9781479954155
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Konferensbidrag (refereegranskat)abstract
- In power microelectronics, the trends towards miniaturization and higher performances result in higher power densities and more heat to be dissipated. In most electronic assembly, thermal interface materials (TIM) help provide a path for heat dissipation but still represent a bottleneck in the total thermal resistance of the system. VA-CNTs mats are typically grown on HR silicon substrate with Al2O3 diffusion barrier layer using Thermal CVD process. In many cases, 'die attach' thermal interface materials need to be electrically conductive and the growth of dense VA-CNT mats on an electrically conductive substrate remains a challenge. This paper presents the growth of dense VA-CNT mats on doped silicon with Al2O3 and TiN diffusion barrier layer. Processes, thermal and electrical characterization of VA-CNTs based thermal interface materials are studied and reported.
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| 5. |
- Fan, X., et al.
(författare)
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Reliability of carbon nanotube bumps for chip on glass application
- 2014
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Ingår i: Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014. - 9781479940264 ; , s. Art. no. 6962753-
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Konferensbidrag (refereegranskat)abstract
- Carbon nanotubes (CNTs) are an ideal candidate material for electronic interconnects due to their extraordinary thermal, electrical and mechanical properties. In this study, densified CNT bumps utilizing the paper-mediated controlled method were applied as the interconnection for chip on glass (COG) applications, and the silicon chip with patterned CNT bumps was then flipped and bonded onto a glass substrate using anisotropic conductive adhesive (ACA) at a bonding pressure of 127.4 Mpa, 170°C for 8 seconds. The electrical properties of the COG were evaluated with the contact resistance of each bump measured using the four-point probe method. Three different structure traces, marked as Trace A, Trace B, and Trace C, were tested, respectively. Thermal cycling (-40 to 85°C, 800 cycles) and damp heat tests (85°C/85% RH, 1000 hours) were also conducted to evaluate the reliability of the CNT-COG structure. The average contact resistance of the samples was recorded during these tests, in which there was no obvious electrical failure observed after both the thermal cycling and damp heat tests. The results of these tests indicated that the COG has good reliability and the CNT bumps have promising potential applications in COG.
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| 6. |
- Jeppson, Kjell, 1947, et al.
(författare)
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Through-Silicon Vias Filled With Densified and Transferred Carbon Nanotube Forests
- 2012
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 33:3, s. 420-422
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Tidskriftsartikel (refereegranskat)abstract
- Through-silicon vias (TSVs) filled with densified and transferred carbon nanotube (CNT) forests are experimentally demonstrated. The filling is achieved by a postgrowth low-temperature transfer process at 200oC instead of direct CNT growth in the vias normally requiring high temperature. A vapor densification method is also applied to densify the as-grown CNT forests, which allows for packing more CNTs in the vias to reduce their resistances. CNT-filled TSVs fabricated based on these two key steps show CMOS compatibility and roughly one order of magnitude reduction in resistivity compared to the TSVs filled with as-grown undensified CNT forests.
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| 7. |
- Jiang, Di, 1983, et al.
(författare)
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A flexible and stackable 3D interconnect system using growth-engineered carbon nanotube scaffolds
- 2017
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Ingår i: Flexible and Printed Electronics. - : IOP Publishing. - 2058-8585. ; 2:2
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Tidskriftsartikel (refereegranskat)abstract
- One of the critical challenges for realizing flexible electronic systems for a wide range of applications is the development of materials for flexible and stackable interconnects. We propose and demonstrate a three-dimensional (3D)interconnect structure embedded in a polymeric substrate using metal-coated carbon nanotube (CNT)scaffolds. By using two different underlayer materials for the catalyst, onestep synthesis of a dual-height CNT interconnect scaffold was realized. The CNT scaffolds serve as flexible cores for both annular metal through-substrate-vias and for horizontal metal interconnect. The 3D-CNT network was fabricated on a silicon substrate, and once the scaffolds were covered by metal, they were embedded in a polymer serving as a flexible substrate after peel-off from the silicon substrate. The 3D-CNT interconnect network was exposed to mechanical bending and stretching tests while monitoring its electrical properties. Even after 300 cycles no significant increase of resistances was found. Electrically there is a trade-off between flexibility and conductivity due to the surface roughness of the scaffold. However, this is to some extent alleviated by the metalized sidewalls giving the horizontal wires a cross-sectional area larger than indicated by their footprint. For gold wires 200 nm thick, measurements indicated a resistivity of 18 μΩ.cm, a value less than one order of magnitude larger than that of bulk gold, and a value that is expected to improve as technology improves. The mechanical properties of the metalized scaffolds were simulated using a finite element model. The potential scale-up capability of the proposed 3D-CNT network was demonstrated by the stacking of two such polymer-embedded interconnect systems.
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| 8. |
- Jiang, Di, 1983, et al.
(författare)
-
Carbon nanotube/solder hybrid structure for interconnect applications
- 2014
-
Ingår i: Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014. - 9781479940264 ; , s. Art. no. 6962751-
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Konferensbidrag (refereegranskat)abstract
- A carbon nanotube (CNT)/Solder hybrid bump structure is proposed in this work in order to overcome the drawbacks of high CNT resistivity while retaining the advantages of CNTs in terms of interconnect reliability. Lithographically defined hollow CNT moulds are grown by thermal chemical vapor deposition (TCVD). The space inside the CNT moulds is filled up with Sn-Au-Cu (SAC) solder spheres of around 10 μm in diameter. This CNT/Solder hybrid material is then reflowed and transferred onto target indium coated substrate. The reflow melts the small solder spheres into large single solder balls thus forming a hybrid interconnect bump together with the surrounding densified CNT walls, which the CNT and the solder serve as resistors in parallel. The electrical resistance of such a CNT/Solder structure is measured to be around 6 folds lower than pure CNT bumps.
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| 9. |
- Jiang, Di, 1983, et al.
(författare)
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Carbon Nanotubes in Electronics Interconnect Applications with a Focus on 3D-TSV Technology
- 2012
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Ingår i: ECS Transactions. - : The Electrochemical Society. - 1938-5862 .- 1938-6737. - 9781607683186 ; 44:1, s. 683-692
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Konferensbidrag (refereegranskat)abstract
- High density electronics integration at the system level, supported by advanced packaging solutions, is expected to be the main driving force for the future shrinking of electronics. One recent focus in the field of electronics packaging is the use of through-silicon-via (TSV) to form three-dimensional (3D) integration. A central task in developing 3D-TSV integration is to build reliable and efficient electrical interconnects for signal transfer and power distribution among the stacked layers. Carbon nanotubes (CNTs) are supposed to be a promising material to build future interconnects due to their many attractive electrical and mechanical properties. This paper reviews the state-of-art in CNT integration technology, with a focus on the 3D-TSV interconnect. The simplicity and manufacturability of fabricating and stacking CNT TSVs presented in this paper indicate a great application potential of CNTs as an interconnection material in future 3D integrated electronics.
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| 10. |
- Jiang, Di, 1983, et al.
(författare)
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Electrical Interconnects Made of Carbon Nanotubes: Applications in 3D Chip Stacking
- 2012
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Ingår i: IMAPS Nordic Annual Conference Proceedings 2012, Helsingor, 2 - 4 September 2012. - 9781622763160 ; , s. 150-159
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Konferensbidrag (refereegranskat)abstract
- High density electronics integration at the system level, supported by advanced packaging solutions, is expected to be the driving force for the future down-scaling of semiconductor electronics. One recent focus in the field of electronic packaging is the use of through-silicon-vias (TSVs) to form three-dimensional (3D) integration. A central task in developing 3D chip integration is to build reliable and efficient 3D electrical interconnects for signal transfer and power distribution among the stacked layers. Carbon nanotubes (CNTs) are proposed to be a promising material to build future interconnects due to their many attractive electrical and mechanical properties. This paper reviews the state-of-art in CNT integration technology, with a focus on the application of 3D chip stacking TSV interconnects. The simplicity and manufacturability of fabricating CNT TSVs presented in this paper indicate a great application potential of CNTs as an interconnection material in future 3D integrated electronics.
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