| 1. |
- Duan, Ningyuan, et al.
(författare)
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Reduction of NiGe/n- and p-Ge Specific Contact Resistivity by Enhanced Dopant Segregation in the Presence of Carbon During Nickel Germanidation
- 2016
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE. - 0018-9383 .- 1557-9646. ; 63:11, s. 4546-4549
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Tidskriftsartikel (refereegranskat)abstract
- This brief explores the specific contact resistivity (rho(c)) of NiGe/n- and p-Ge contacts with and without carbon pregermanidation implantation. It is found that in the presence of carbon, not only the thermal stability of NiGe films is improved, but also the rho(c) of the NiGe/n- and p-Ge contacts is reduced remarkably due to enhanced phosphorus (P) and boron (B) dopant segregation (DS) at the NiGe/Ge interface after nickel germanidation. At 500 degrees C germanidation temperature, the.c values are reduced from 1.1 x 10(-4) Omega-cm(2) and 2.9 x 10(-5) Omega-cm(2) for NiGe/n- and p-Ge contacts without carbon to 7.3 x 10(-5) Omega-cm(2) and 1.4 x 10(-5) Omega-cm(2) for their counterparts with carbon, respectively.
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| 2. |
- Wang, Xiaolei, et al.
(författare)
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Physically Based Evaluation of Effect of Buried Oxide on Surface Roughness Scattering Limited Hole Mobility in Ultrathin GeOI MOSFETs
- 2017
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Ingår i: IEEE Transactions on Electron Devices. - : IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC. - 0018-9383 .- 1557-9646. ; 64:6, s. 2611-2616
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents a numerical simulation study investigating the effect of buried oxide on surface roughness scattering limited hole mobility (mu(SR)) in ultrathin germanium-on-insulator (GeOI) MOSFETs, for the first time. The simulation considers wave function penetration at channel/oxide interface and nonlinear dependence of scattering matrix element on surface fluctuation. Three types of buried oxide materials are compared (GeO2, SiO2, and Si3N4). The mu(SR) increases in the order of SiO2 < GeO2 < Si3N4. This dependence of mu(SR) on buried oxide material is due to surface fluctuation scattering from backside Ge/buried oxide interface. Our simulation results show that Si3N4 and GeO2 are beneficial as buried oxide for mobility enhancement in GeOI MOSFETs, compared with conventional SiO2 as buried oxide. Our findings provide an insight into further improving mobility characteristic.
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| 3. |
- Luo, Jun, et al.
(författare)
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Effects of carbon pre-silicidation implant into Si substrate on NiSi
- 2014
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 120, s. 178-181
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Tidskriftsartikel (refereegranskat)abstract
- In this work, the effects of carbon pre-silicidation implant into Si(1 0 0) substrate on NiSi were investigated. NiSi films with carbon pre-silicidation implant to different doses were characterized by means of sheet resistance measurements, X-ray diffraction, scanning electron microscopy (SEM), planar view transmission electron microscopy (TEM) and second ion mass spectroscopy (SIMS). The presence of C is found to indeed significantly improve the thermal stability of NiSi as well as tends to change the preferred orientations of polycrystalline NiSi. The homogeneously distributed C at NiSi grain boundaries and C peak at NiSi/Si interface is ascribed to the improved thermal stability of NiSi. More importantly, the dose of carbon pre-silicidation implant also plays a key role in the formation of NiSi, which is suggested not to exceed a critical value about 5 x 10(15) cm(-2) in practical application in accordance with the results achieved in this work. (C) 2013 Elsevier B.V. All rights reserved.
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| 4. |
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| 5. |
- Luo, Jun, et al.
(författare)
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Variation of Schottky barrier height induced by dopant segregation monitored by contact resistivity measurements
- 2014
-
Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 120, s. 174-177
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Tidskriftsartikel (refereegranskat)abstract
- Change of contact resistivity (rho(c)) is monitored for evaluation of Schottky barrier height (SBH) variation induced by dopant segregation (DS). This method is particularly advantageous for metal-semiconductor contacts of small SBH, as it neither requires low-temperature measurement needed in current-voltage characterization of Schottky diodes nor is affected by reverse leakage current often troubling capacitance-voltage characterization. With PtSi contact to both n- and p-type diffusion regions, and the use of opposite or alike dopants implant into pre-formed PtSi films followed by drive-in anneal at different temperatures to induce DS at PtSi/Si interface, the formation of interfacial dipole is confirmed as the responsible cause for modification of effective SBHs thus the increase or decrease of rho(c). A tentative explanation for the change of contact resistivity based on interfacial dipole theory is provided in this work. Influences and interplay of interfacial dipole and space charge on effective SBH are also discussed. (C) 2013 Elsevier B.V. All rights reserved.
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| 6. |
- Wang, Guilei, et al.
(författare)
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Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)
- 2020
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Ingår i: Journal of materials science. Materials in electronics. - : Springer Science and Business Media LLC. - 0957-4522 .- 1573-482X. ; 31, s. 26-33
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.
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| 7. |
- Wang, Guilei, et al.
(författare)
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Integration of Highly Strained SiGe in Source and Drain with HK and MG for 22 nm Bulk PMOS Transistors
- 2017
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Ingår i: Nanoscale Research Letters. - : Springer. - 1931-7573 .- 1556-276X. ; 12
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the integration of SiGe selective epitaxy on source/drain regions and high-k and metal gate for 22 nm node bulk pMOS transistors has been presented. Selective Si1-xGex growth (0.35 <= x <= 0.40) with boron concentration of 1-3 x 10(20) cm(-3) was used to elevate the source/drain. The main focus was optimization of the growth parameters to improve the epitaxial quality where the high-resolution x-ray diffraction (HRXRD) and energy dispersive spectrometer (EDS) measurement data provided the key information about Ge profile in the transistor structure. The induced strain by SiGe layers was directly measured by x-ray on the array of transistors. In these measurements, the boron concentration was determined from the strain compensation of intrinsic and boron-doped SiGe layers. Finally, the characteristic of transistors were measured and discussed showing good device performance.
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| 8. |
- Wang, Guilei, et al.
(författare)
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Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology
- 2016
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Ingår i: Microelectronic Engineering. - : Elsevier. - 0167-9317 .- 1873-5568. ; 163, s. 49-54
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Tidskriftsartikel (refereegranskat)abstract
- In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics.
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| 9. |
- Zhao, Xuewei, et al.
(författare)
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Design impact on the performance of Ge PIN photodetectors
- 2020
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Ingår i: Journal of materials science. Materials in electronics. - : Springer. - 0957-4522 .- 1573-482X. ; 31:1, s. 18-25
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Tidskriftsartikel (refereegranskat)abstract
- This article presents the impact of epitaxial quality, contact resistance and profile of Ge PIN photodetectors (PDs) on dark current and responsivity. The PD structures were processed with either selectively grown Ge with integrated waveguides on SOI wafer or globally grown Ge on the entire wafer. The contact resistance was lowered by introducing NiGe layer prior to the metallization. The n-type doped Ge PIN structure was formed by ion implantation and the contact resistivity was estimated to 2.6x10(-4) ohm cm(2). This value is rather high and it is believed to be due to fomation of defects during implantation. The results show a minor difference in dark currents for selectively and globally grown PDs but in both types, it depends on detector area and the epitaxial quality of Ge. For example, the threading dislocation density (TDD) in non-selectively grown PDs with thickness of 1 mu m was estimated to be 10(6) cm(-2) yielding relatively low dark currents while it dramatically changes for PDs with thinner Ge layers where TDD increases to 10(8) cm(-2) and the dark current levels increase almost by 1.5 magnitude. Surprisingly, for selectively grown PDs with Ge thickness of 500 nm, TDD was still low resulting in low dark currents. The dark current densities at -1 V bias of non-selectively and selectively grown PDs with optimized profile were measured to be 5 mA/cm(2) and 47 mA/cm(2), respectively, while the responsivity of these detectors were 0.17 A/W and 0.46 A/W at lambda similar to 1.55 mu m, respectively. Excellent performance for selectively grown PD shows an appropriate choice for detection of 1.55 mu m wavelength.
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| 10. |
- Fu, Chaochao, et al.
(författare)
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Schottky Barrier Height Tuning via the Dopant Segregation Technique through Low-Temperature Microwave Annealing
- 2016
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Ingår i: Materials. - : MDPI AG. - 1996-1944. ; 9:5
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Tidskriftsartikel (refereegranskat)abstract
- The Schottky junction source/drain structure has great potential to replace the traditional p/n junction source/drain structure of the future ultra-scaled metal-oxide-semiconductor field effect transistors (MOSFETs), as it can form ultimately shallow junctions. However, the effective Schottky barrier height (SBH) of the Schottky junction needs to be tuned to be lower than 100 meV in order to obtain a high driving current. In this paper, microwave annealing is employed to modify the effective SBH of NiSi on Si via boron or arsenic dopant segregation. The barrier height decreased from 0.4–0.7 eV to 0.2–0.1 eV for both conduction polarities by annealing below 400 °C. Compared with the required temperature in traditional rapid thermal annealing, the temperature demanded in microwave annealing is ~60 °C lower, and the mechanisms of this observation are briefly discussed. Microwave annealing is hence of high interest to future semiconductor processing owing to its unique capability of forming the metal/semiconductor contact at a remarkably lower temperature.
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