| 1. |
- Egard, Mikael, et al.
(författare)
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Frequency Modulation in mm-Wave InGaAs MOSFET/RTD Wavelet Generators
- 2013
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Ingår i: 2013 International Conference on Indium Phosphide and Related Materials (IPRM). - 1092-8669. ; , s. 1-2
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Konferensbidrag (refereegranskat)abstract
- Co-integration of an InGaAs MOSFET and an RTD is performed to realize a wavelet generator. The large transconductance of the MOSFET (1.9 mS/mu m) is used to switch the current in an oscillator circuit and coherent wavelets down to 41 ps are generated in the frequency domain of 50 to 100 GHz. The lowest power consumption measured is 1.9 pJ/pulse. It is found that the supply bias can be used to modulate the center frequency of the wavelets.
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| 2. |
- Egard, Mikael, et al.
(författare)
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High Transconductance Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFET
- 2011
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Ingår i: 2011 IEEE International Electron Devices Meeting (IEDM). - 9781457705052
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Konferensbidrag (refereegranskat)abstract
- In this paper we present a 55 nm gate length In0.53Ga0.47As MOSFET with extrinsic transconductance of 1.9 mS/mu m and on-resistance of 199 Omega mu m. T he self-aligned MOSFET is formed using metalorganic chemical vapor deposition regrowth of highly doped source and drain access regions. The fabricated 140 nm gate length devices shows a low subthreshold swing of 79 mV/decade, which is attributed to the described low temperature gate-last process scheme.
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| 3. |
- Egard, Mikael, et al.
(författare)
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Self-aligned gate-last surface channel In0.53Ga0.47As MOSFET with selectively regrown source and drain contact layers
- 2011
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Ingår i: 69th Device Research Conference, DRC 2011 - Conference Digest. - 9781612842417
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Konferensbidrag (refereegranskat)abstract
- III-V MOSFETs are currently being considered as a candidate for future high performance transistors [1]. In particular, In1-xGaxAs compounds are investigated for application in digital logic due to their advantageous electronic properties [2]. III-V technologies may be introduced beyond the 22 nm node, which will require a self aligned III/V device architecture as well as integration of high-¿ gate oxides.
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| 4. |
- Fröberg, Linus, et al.
(författare)
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Vertical InAs nanowire wrap-gate FETs
- 2006
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Ingår i: Book of abstracts: Semicond Nanowires Symp, Eindhoven, The Netherlands (2006).
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Konferensbidrag (refereegranskat)
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| 5. |
- Ohlsson, Lars, et al.
(författare)
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Admittance Matching of 60 GHz Rectangular Dielectric Resonator Antennas for Integrated Impulse Radio
- 2010
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Ingår i: [Host publication title missing]. ; , s. 253-256
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Konferensbidrag (refereegranskat)abstract
- Methods to achieve admittance matching of rectangular dielectric resonator antennas intended for 60~GHz impulse radio are reported. The motivation is to find a suitable antenna that may be integrated in the V-band gated tunnel diode wavelet generator, replacing its tank circuit and forming a low complexity transmitter. Probed one- and two-port scattering parameter measurements have been performed to characterise the fabricated antennas. Changing the feed structure from a tapered dipole to an offset fed and tapered slot, a change from capacitive to inductive characteristics is observed, and the matching to the gated tunnel diode is improved. Deembedded admittance resonance frequencies of fabricated antennas were found at 53.6 and 52.2~GHz for dipole and slot fed antennas, respectively. Characterising the transmission link between dipole fed antennas, a maximum antenna gain of 10.5~dBi and a 3~dB power bandwidth of 1.5~GHz were found at 53.3~GHz.
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| 6. |
- Ohlsson, Lars, et al.
(författare)
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First InGaAs lateral nanowire MOSFET RF noise measurements and model
- 2017
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Ingår i: 75th Annual Device Research Conference, DRC 2017. - 9781509063277
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Konferensbidrag (refereegranskat)abstract
- The first radio frequency (RF) noise measurements on lateral nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and a noise model are presented. We have characterized the RF noise and scattering parameters of an indium gallium arsenide (InGaAs) device. A fitted model yields extrapolated ft = 316 GHz current gain cutoff and fmax = 166 GHz maximum oscillation frequency. This device technology is being developed for millimeter wave circuit implementations, targeting a 94 GHz carrier frequency. The modeled intrinsic Fmin < 1dB minimum noise figure obtained promises performance at the target band, given reduction of gate parasitics. In any wireless system, noise and bandwidth limits the performance. Understanding of RF noise in nanowire MOSFET devices is thereby key for realization of future radar and communications systems.
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| 7. |
- Roll, Guntrade, et al.
(författare)
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RF reliability of gate last InGaAs nMOSFETs with high-k dielectric
- 2013
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Ingår i: 2013 IEEE International Integrated Reliability Workshop Final Report, IIRW 2013. - 9781479903504 ; , s. 38-41
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Konferensbidrag (refereegranskat)abstract
- A complete reliability study of the high-frequency characteristics for nMOSFETs on InGaAs channel with Al2O3/HfO2 gate dielectric is presented. DC gate voltage stress causes an increase in the transconductance frequency dispersion. Stress induced border traps degrade the maximum DC-transconductance, but do not react at high frequencies. The main degradation characteristics of the high-frequency measurements can be modeled by the threshold voltage related transconductance shift. The maximum of the cut-off frequency is shifted with stress to higher or lower gate biases, but not decreased.
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| 8. |
- Wernersson, Lars-Erik, et al.
(författare)
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Wrap-gated InAs nanowire field-effect transistor
- 2005
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Ingår i: International Electron Devices Meeting 2005. - 078039268X ; , s. 273-276
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Konferensbidrag (refereegranskat)abstract
- Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design
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| 9. |
- Ärlelid, Mats, et al.
(författare)
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60 GHz impulse radio measurements
- 2011
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Ingår i: 2011 IEEE International Conference on Ultra-Wideband (ICUWB). - 2162-6588. - 9781457717635 ; , s. 536-540
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Konferensbidrag (refereegranskat)abstract
- The bit-error rate of a 60 GHz wireless impulse radio link is investigated at a bit-rate of 4 Gbps using on-off keying. The measurement results show that it is possible to have a BER below 10(-12), and the measured BER vs. E-b/N-o is approximately 1 dB from the theoretical value. The reliability of the wideband 60 GHz wavelet generator is furthermore confirmed by studying the number of faulty wavelets generated, and the circuit performance is characterized. The wavelet generator consumes 30 mW and may generate signals with bandwidth exceeding 25 GHz, which may be used to investigate the channel properties at 60 GHz.
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| 10. |
- Andric, Stefan, et al.
(författare)
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Design of III-V Vertical Nanowire MOSFETs for Near-Unilateral Millimeter-Wave Operation
- 2021
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Ingår i: EuMIC 2020 - 2020 15th European Microwave Integrated Circuits Conference. - 9782874870606 ; , s. 85-88
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Konferensbidrag (refereegranskat)abstract
- Vertical nanowire MOSFETs exhibit asymmetric gate capacitances, allowing for their independent engineering to improve device high frequency performance. Minimizing gate-drain parasitic capacitance with the use of a vertical sidewall spacer enables universal feedback neutralization and a unilateral circuit design. For vertical spacer thickness above 20 nm, the gate-drain capacitance variability is reduced. Device technology is verified by simulation of 60 GHz three-stage low-noise amplifier. The amplifier exhibits 10 dB gain and 6.9 dB noise figure. The noise figure can be further reduced to 5.9 dB by combining several feedback techniques. The use of capacitance minimization reduces circuit sensitivity to device variation, demonstrating the potential of this technology in implementation of mm-wave communication and sensing systems.
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