| 1. |
- Berg, Martin, et al.
(författare)
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A transmission line method for evaluation of vertical InAs nanowire contacts
- 2015
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Ingår i: Applied Physics Letters. - : AIP Publishing. - 0003-6951 .- 1077-3118. ; 107:23
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we present a method for metal contact characterization to vertical semiconductor nanowires using the transmission line method (TLM) on a cylindrical geometry. InAs nanowire resistors are fabricated on Si substrates using a hydrogen silsesquioxane (HSQ) spacer between the bottom and top contact. The thickness of the HSQ is defined by the dose of an electron beam lithography step, and by varying the separation thickness for a group of resistors, a TLM series is fabricated. Using this method, the resistivity and specific contact resistance are determined for InAs nanowires with different doping and annealing conditions. The contacts are shown to improve with annealing at temperatures up to 300 degrees C for 1min, with specific contact resistance values reaching down to below 1 Omega mu m(2). (C) 2015 AIP Publishing LLC.
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| 2. |
- Berg, Martin, et al.
(författare)
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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
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Tidskriftsartikel (refereegranskat)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
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| 3. |
- Berg, Martin, et al.
(författare)
-
InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.
- 2014
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 25:48
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Tidskriftsartikel (refereegranskat)abstract
- Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a [Formula: see text] cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.
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| 4. |
- Berg, Martin, et al.
(författare)
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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
- 2016
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Ingår i: Technical Digest - International Electron Devices Meeting, IEDM. - 9781467398930 ; 2016-February
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Konferensbidrag (refereegranskat)abstract
- In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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| 5. |
- Berg, Martin, et al.
(författare)
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Single Balanced Down-Conversion Mixer Utilizing Indium Arsenide Nanowire MOSFETs
- 2014
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Ingår i: 26th International Conference on Indium Phosphideand Related Materials (IPRM). - 1092-8669.
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Konferensbidrag (refereegranskat)abstract
- We have fabricated single balanced down-conversion mixer circuits using InAs nanowire MOSFETs as both active and passive devices. This is achieved by a combination of electron beam lithography and UV-lithography with a line width of 12 mu m. The circuits exhibit a low frequency voltage conversion gain of 6 dB, a -3 dB cutoff frequency of 2 GHz and a power consumption of 3.8 mW, while operating at a supply voltage of 1.5 V. The circuits retain circuit functionality even for a supply voltage of 1 V.
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| 6. |
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| 7. |
- Johansson, Sofia, et al.
(författare)
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High frequency vertical InAs nanowire MOSFETs integrated on Si substrates
- 2012
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Ingår i: Physica Status Solidi. C, Current Topics in Solid State Physics. - : Wiley. - 1610-1634. ; 9:2, s. 350-353
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Tidskriftsartikel (refereegranskat)abstract
- RF and DC characterization of vertical InAs nanowire MOSFET on Si substrates are presented. Nanowire arrays are epitaxially integrated on Si substrates by use of a thin InAs buffer layer. For device fabrication, high-k HfO2 gate dielectric and wrap-gates are used. Post-deposition annealing of the high-k is evaluated by comparing one annealed and one not-annealed sample. The annealed sample show better DC characteristics in terms of transconductance, g(m) = 155 mS/mm, and on-current, I-on = 550 mA/mm. Box plots of on-current, on-resistance and transconductance for all 190-nanowire-array transistors on the annealed sample suggest that the electrical properties of the nanowires are preserved when scaling the nanowire diameter. Finally, high frequency characterisation yields a unity current gain cut-off frequency of f(t) = 9.3 GHz for the annealed sample and f(t) = 2.0 GHz for the not-annealed sample. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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| 8. |
- Johansson, Sofia, et al.
(författare)
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RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates
- 2011
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 59:10, s. 2733-2738
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Tidskriftsartikel (refereegranskat)abstract
- We present dc and RF characterization of InAs nanowire field-effect transistors (FETs) heterogeneously integrated on Si substrates in a geometry suitable for circuit applications. The FET consists of an array of 182 vertical InAs nanowires with about 6-nm HfO high-gate dielectric and a wrap-gate length of 250 nm. The transistor has a transconductance of 155 mS/mm and an on-current of 550 mA/mm at a gate voltage of 1.5 V and a drain voltage of 1 V. S-parameter measurements yield an extrinsic cutoff frequency of 9.3 GHz and a extrinsic maximum oscillation frequency of 14.3 GHz.
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| 9. |
- Persson, Karl-Magnus, et al.
(författare)
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1/f-noise in Vertical InAs Nanowire Transistors
- 2013
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Ingår i: 2013 International Conference on Indium Phosphide and Related Materials (IPRM). - 1092-8669. ; , s. 1-2
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Konferensbidrag (refereegranskat)abstract
- The material quality at high-k interfaces are a major concern for FET devices. We study the effect on two types of InAs nanowire (NW) transistors and compare their characteristics. It is found that by introducing an inner layer of Al2O3 at the high-kappa interface, the low frequency noise (LFN) performance regarding gate voltage noise spectral density, S-Vg, is improved by one order of magnitude per unit gate area.
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| 10. |
- Persson, Karl-Magnus, et al.
(författare)
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Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates
- 2013
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 60:9, s. 2761-2767
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Tidskriftsartikel (refereegranskat)abstract
- This paper presents DC and RF characterization as well as modeling of vertical InAs nanowire MOSFETs with LG = 200 nm and Al2O3/HfO2 high-κ dielectric. Measurements at VDS = 0.5 V show that high transconductance (gm = 1.37 mS/μm), high drive current (IDS = 1.34 mA/μm), and low on-resistance (RON = 287 Ωμm) can be realized using vertical InAs nanowires on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, SVG·LG·WG, is determined to be lowered one order of magnitude compared to similar devices with a high-κ film consisting of HfO2 only. Additionally, with a virtual source model we are able to determine the intrinsic transport properties. These devices (LG = 200 nm) show a high injection velocity (vinj = 1.7·107 cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.
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