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| 2. |
- Gorji, Sepideh, et al.
(författare)
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Uniform and position-controlled InAs nanowires on 2('') Si substrates for transistor applications.
- 2012
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 23:1
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Tidskriftsartikel (refereegranskat)abstract
- This study presents a novel approach for indirect integration of InAs nanowires on 2('') Si substrates. We have investigated and developed epitaxial growth of InAs nanowires on 2('') Si substrates via the introduction of a thin yet high-quality InAs epitaxial layer grown by metalorganic vapor phase epitaxy. We demonstrate well-aligned nanowire growth including precise position and diameter control across the full wafer using very thin epitaxial layers (<300 nm). Statistical analysis results performed on the grown nanowires across the 2('') wafer size verifies our full control on the grown nanowire with 100% growth yield. From the crystallographic viewpoint, these InAs nanowires are predominantly of wurtzite structure. Furthermore, we show one possible device application of the aforementioned structure in vertical wrap-gated field-effect transistor geometry. The vertically aligned InAs nanowires are utilized as transistor channels and the InAs epitaxial layer is employed as the source contact. A high uniformity of the device characteristics for numerous transistors is further presented and RF characterization of these devices demonstrates an f(t) of 9.8 GHz.
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| 3. |
- Johansson, Sofia, et al.
(författare)
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High frequency vertical InAs nanowire MOSFETs integrated on Si substrates
- 2012
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Ingår i: Physica Status Solidi. C, Current Topics in Solid State Physics. - : Wiley. - 1610-1634. ; 9:2, s. 350-353
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Tidskriftsartikel (refereegranskat)abstract
- RF and DC characterization of vertical InAs nanowire MOSFET on Si substrates are presented. Nanowire arrays are epitaxially integrated on Si substrates by use of a thin InAs buffer layer. For device fabrication, high-k HfO2 gate dielectric and wrap-gates are used. Post-deposition annealing of the high-k is evaluated by comparing one annealed and one not-annealed sample. The annealed sample show better DC characteristics in terms of transconductance, g(m) = 155 mS/mm, and on-current, I-on = 550 mA/mm. Box plots of on-current, on-resistance and transconductance for all 190-nanowire-array transistors on the annealed sample suggest that the electrical properties of the nanowires are preserved when scaling the nanowire diameter. Finally, high frequency characterisation yields a unity current gain cut-off frequency of f(t) = 9.3 GHz for the annealed sample and f(t) = 2.0 GHz for the not-annealed sample. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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| 4. |
- Johansson, Sofia, et al.
(författare)
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RF Characterization of Vertical InAs Nanowire Wrap-Gate Transistors Integrated on Si Substrates
- 2011
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Ingår i: IEEE Transactions on Microwave Theory and Techniques. - 0018-9480. ; 59:10, s. 2733-2738
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Tidskriftsartikel (refereegranskat)abstract
- We present dc and RF characterization of InAs nanowire field-effect transistors (FETs) heterogeneously integrated on Si substrates in a geometry suitable for circuit applications. The FET consists of an array of 182 vertical InAs nanowires with about 6-nm HfO high-gate dielectric and a wrap-gate length of 250 nm. The transistor has a transconductance of 155 mS/mm and an on-current of 550 mA/mm at a gate voltage of 1.5 V and a drain voltage of 1 V. S-parameter measurements yield an extrinsic cutoff frequency of 9.3 GHz and a extrinsic maximum oscillation frequency of 14.3 GHz.
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| 5. |
- Johansson, Sofia, et al.
(författare)
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Temperature and annealing effects on InAs nanowire MOSFETs
- 2011
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Ingår i: Microelectronic Engineering. - : Elsevier BV. - 0167-9317 .- 1873-5568. ; 88:7, s. 1105-1108
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Konferensbidrag (refereegranskat)abstract
- We report on temperature dependence on the drive current as well as long-term effects of annealing in vertical InAs nanowire Field-Effect Transistors. Negatively charged traps in the HfO2 gate dielectric are suggested as one major factor in explaining the effects observed in the transistor characteristics. An energy barrier may be correlated with an un-gated InAs nanowire region covered with HfO2 and the effects of annealing may be explained by changed charging on defects in the oxide. Initial simulations confirm the general effects on the I-V characteristics by including fixed charge. (c) 2011 Elsevier B.V. All rights reserved.
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| 6. |
- Gorji, Sepideh, et al.
(författare)
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Growth of InAs/InP core-shell nanowires with various pure crystal structures.
- 2012
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 23:28
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Tidskriftsartikel (refereegranskat)abstract
- We have studied the epitaxial growth of an InP shell on various pure InAs core nanowire crystal structures by metal-organic vapor phase epitaxy. The InP shell is grown on wurtzite (WZ), zinc-blende (ZB), and {111}- and {110}-type faceted ZB twin-plane superlattice (TSL) structures by tuning the InP shell growth parameters and controlling the shell thickness. The growth results, particularly on the WZ nanowires, show that homogeneous InP shell growth is promoted at relatively high temperatures (∼500 °C), but that the InAs nanowires decompose under the applied conditions. In order to protect the InAs core nanowires from decomposition, a short protective InP segment is first grown axially at lower temperatures (420-460 °C), before commencing the radial growth at a higher temperature. Further studies revealed that the InP radial growth rate is significantly higher on the ZB and TSL nanowires compared to WZ counterparts, and shows a strong anisotropy in polar directions. As a result, thin shells were obtained during low temperature InP growth on ZB structures, while a higher temperature was used to obtain uniform thick shells. In addition, a schematic growth model is suggested to explain the basic processes occurring during the shell growth on the TSL crystal structures.
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| 7. |
- Gorji, Sepideh, et al.
(författare)
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High quality InAs and GaSb thin layers grown on Si (111)
- 2011
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Ingår i: Journal of Crystal Growth. - : Elsevier BV. - 0022-0248. ; 332:1, s. 12-16
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Tidskriftsartikel (refereegranskat)abstract
- We have investigated growth of thin epitaxial layers of InAs on Si (1 1 1) substrates by metalorganic vapor phase epitaxy (MOVPE) and successfully grown GaSb layers on InAs. Furthermore, we have studied the effect of growth temperature and material flow on the nucleation stage and also nucleated GaSb nanowires on the underlying GaSb layer. The InAs layers are grown by a standard two-step growth approach. The main parameter under investigation is the effect of incorporating more nucleation layers into the growth process. The addition of more nucleation layers clearly correlates with the surface morphology and quality of the resulting InAs layer. Morphological and structural characterizations prove that a perfect quality InAs layer is achieved by incorporating 4 nucleation layers. Deposited layers with 250 nm thickness and 0.4 nm atomic step roughness have a mobility of 2400 cm(2)/Vs and a carrier concentration of 2.7 x 10(18) cm(-3). Moreover, we have utilized the InAs film to grow a GaSb layer and observed atomic step roughness for a thin film of similar to 300 nm. Finally we demonstrate the growth of GaSb nanowires on the GaSb layer. (C) 2011 Elsevier B.V. All rights reserved.
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| 8. |
- Gorji, Sepideh, et al.
(författare)
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Highly controlled InAs nanowires on Si(111) wafers by MOVPE
- 2012
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Ingår i: physica status solidi (c). - : Wiley. - 1862-6351 .- 1610-1642. ; 9:2
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Konferensbidrag (refereegranskat)abstract
- We have investigated epitaxial growth of InAs layers on 2 '' Si (111) substrates by Metalorganic Vapor Phase Epitaxy. Structural and morphological characterization results confirm high quality of the obtained thin layers. Then, we have utilized the InAs layers as substrates for InAs nanowire growth and Au nanoparticles were lithographically defined at various positions on the surface. Statistical analysis performed on the InAs nanowires grown on 2 '' substrates demonstrates our full control on the position, diameter and vertical alignment across the wafer. One possible device application of the aforementioned structure is wrap-gated Metal-Oxide-Semiconductor Field-Effect Transistors where the InAs layer is employed as the bottom contact and the InAs nanowires act as channel materials. [GRAPHICS] SEM image of part of epitaxially grown InAs nanowires on the InAs layer on 2" Si substrate. The scale bar is 50 mu m. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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