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Träfflista för sökning "WFRF:(Wernersson Lars Erik) ;pers:(Jansson Kristofer)"

Sökning: WFRF:(Wernersson Lars Erik) > Jansson Kristofer

  • Resultat 1-8 av 8
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2.
  • Jansson, Kristofer, et al. (författare)
  • Amplifier Design Using Vertical InAs Nanowire MOSFETs
  • 2016
  • Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 63:6, s. 2353-2359
  • Tidskriftsartikel (refereegranskat)abstract
    • In this paper, an amplifier design using ballistic vertical InAs nanowire (NW) transistors is investigated, focusing on a basic common-source amplifier. The maximum power gain at 90 GHz is evaluated for different NW transistor architectures together with the power dissipation. The linearity of the amplifier is evaluated by estimating the IIP3 and 1-dB compression points. Furthermore, the impact of the parasitic capacitances and resistances is quantified and it is demonstrated that the gain may be increased by a cascode design. It is concluded that a power gain exceeding 20 dB at 90 GHz may be achieved by a common-source amplifier based on an InAs NW transistor architecture. A power consumption below 1 mW is possible, while still maintaining a high power gain. Furthermore, IIP3 exceeding 10 dBm is predicted. The combination of these qualities makes the NW transistor architecture an attractive prospect for low-power amplifiers at millimeter wave frequencies.
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3.
  • Jansson, Kristofer, et al. (författare)
  • Ballistic modeling of InAs nanowire transistors
  • 2016
  • Ingår i: Solid-State Electronics. - : Elsevier BV. - 0038-1101. ; 115, s. 47-53
  • Tidskriftsartikel (refereegranskat)abstract
    • In this work, the intrinsic performance of InAs nanowire transistors is evaluated in the ballistic limit. A self-consistent Schrodinger-Poisson solver is utilized in the cylindrical geometry, while accounting for conduction band non-parabolicity. The transistor characteristics are derived from simulations of ballistic transport within the nanowire. Using this approach, the performance is calculated for a continuous range of nanowire diameters and the transport properties are mapped. A transconductance exceeding 4 S/mm is predicted at a gate overdrive of 0.5 V and it is shown that the performance is improved with scaling. Furthermore, the influence from including self-consistency and non-parabolicity in the band structure simulations is quantified. It is demonstrated that the effective mass approximation underestimates the transistor performance due to the highly non-parabolic conduction band in InAs. Neglecting self-consistency severely overestimates the device performance, especially for thick nanowires. The error introduced by both of these approximations gets increasingly worse under high bias conditions. (C) 2015 Elsevier Ltd. All rights reserved.
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4.
  • Jansson, Kristofer, et al. (författare)
  • Intrinsic Performance of InAs Nanowire Capacitors
  • 2014
  • Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 61:2, s. 452-459
  • Tidskriftsartikel (refereegranskat)abstract
    • The intrinsic properties of vertical InAs nanowire (NW) capacitors are investigated. The band structure is simulated using a Schrödinger-Poisson solver, taking the conduction band nonparabolicity into account. This is combined with a distributed RC model to simulate the current-voltage characteristics. It is found that the influence from the nonparabolicity is substantial for devices with a small nanowire diameter, resulting in an increased carrier concentration, a shift in the threshold voltage, and a higher intrinsic capacitance. These NW capacitors may be a suitable alternative in high frequency applications approaching 100 GHz, while maintaining a quality factor above 100.
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5.
  • Jansson, Kristofer, et al. (författare)
  • Performance Evaluation of III–V Nanowire Transistors
  • 2012
  • Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 59:9, s. 2375-2382
  • Tidskriftsartikel (refereegranskat)abstract
    • III–V nanowire (NW) transistors are an emerging technology with the prospect of high performance and low power dissipation. Performance evaluations of these devices, however, have focused mostly on the intrinsic properties of the NW, excluding any parasitic elements. In this paper, a III–V NW transistor architecture is investigated, based on a NW array with a realistic footprint. Based on scaling rules for the structural parameters, 3-D representations of the transistor are generated, and the parasitic capacitances are calculated. A complete optimization of the structure is performed based on the RF performance metrics fT and fmax, employing intrinsic transistor data combined with calculated parasitic capacitances and resistances. The result is a roadmap of optimized transistor structures for a set of technology nodes, with gate lengths down to the 10-nm-length scale. For each technology node, the performance is predicted, promising operation in the terahertz regime. The resulting roadmap has implications as a reference both for benchmarking and for device fabrication.
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6.
  • Persson, Karl-Magnus, et al. (författare)
  • Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates
  • 2013
  • Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 60:9, s. 2761-2767
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents DC and RF characterization as well as modeling of vertical InAs nanowire MOSFETs with LG = 200 nm and Al2O3/HfO2 high-κ dielectric. Measurements at VDS = 0.5 V show that high transconductance (gm = 1.37 mS/μm), high drive current (IDS = 1.34 mA/μm), and low on-resistance (RON = 287 Ωμm) can be realized using vertical InAs nanowires on Si substrates. By measuring the 1/f-noise, the gate area normalized gate voltage noise spectral density, SVG·LG·WG, is determined to be lowered one order of magnitude compared to similar devices with a high-κ film consisting of HfO2 only. Additionally, with a virtual source model we are able to determine the intrinsic transport properties. These devices (LG = 200 nm) show a high injection velocity (vinj = 1.7·107 cm/s) with a performance degradation for array FETs predominantly due to an increase in series resistance.
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8.
  • Wu, Jun, et al. (författare)
  • RF Characterization of Vertical Wrap-Gated InAs/High-κ Nanowire Capacitors
  • 2016
  • Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 63:2, s. 584-589
  • Tidskriftsartikel (refereegranskat)abstract
    • This paper presents RF as well as low-frequency capacitance–voltage (C–V) characterization of vertical wrap-gated InAs/high-κ nanowire MOS capacitors. A full equivalent circuit model for traps is used to fit the low-frequency C–V characteristics, from which the interface trap density (Dit) and border trap density (Nbt) are evaluated separately. The results show comparable Nbt but far lower Dit (<10E12 eV−1cm−2 near the conduction band edge) for a nanowire MOS gate-stack compared with planar references. In the RF domain, the influence of nanowire series resistances become significant, and by introducing a distributed RC-model, the nanowire resistivity (ρnw) is evaluated from the capacitance data as a function of the gate bias. An ON/OFF ρnw ratio of 10E−2 is obtained for the best device. Using the measured data, the quality factor is finally evaluated both for fabricated and ideal capacitors. The results agree well with simulated data.
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  • Resultat 1-8 av 8

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