| 1. |
- Egard, Mikael, et al.
(författare)
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High-Frequency Performance of Self-Aligned Gate-Last Surface Channel In0.53Ga0.47As MOSFET
- 2012
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 33:3, s. 369-371
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Tidskriftsartikel (refereegranskat)abstract
- We have developed a self-aligned L-g = 55 nm In-0.53 Ga-0.47 As MOSFET incorporating metal-organic chemical vapor deposition regrown n(++) In0.6Ga0.4As source and drain regions, which enables a record low on-resistance of 199 Omega mu m. The regrowth process includes an InP support layer, which is later removed selectively to the n(++) contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing f(max) of 292 GHz and f(t) of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/mu m and a high extrinsic transconductance of 1.9 mS/mu m. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.
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| 2. |
- Berg, Martin, et al.
(författare)
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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- 2016
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Ingår i: IEEE Electron Device Letters. - 0741-3106. ; 37:8, s. 966-969
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Tidskriftsartikel (refereegranskat)abstract
- Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
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| 3. |
- Berg, Martin, et al.
(författare)
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InAs nanowire MOSFETs in three-transistor configurations: single balanced RF down-conversion mixers.
- 2014
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Ingår i: Nanotechnology. - : IOP Publishing. - 0957-4484 .- 1361-6528. ; 25:48
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Tidskriftsartikel (refereegranskat)abstract
- Integration of III-V semiconductors on Si substrates allows for the realization of high-performance, low power III-V electronics on the Si-platform. In this work, we demonstrate the implementation of single balanced down-conversion mixer circuits, fabricated using vertically aligned InAs nanowire devices on Si. A thin, highly doped InAs buffer layer has been introduced to reduce the access resistance and serve as a bottom electrode. Low-frequency voltage conversion gain is measured up to 7 dB for a supply voltage of 1.5V. Operation of these mixers extends into the GHz regime with a [Formula: see text] cut-off frequency of 2 GHz, limited by the optical lithography system used. The circuit dc power consumption is measured at 3.9 mW.
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| 4. |
- Berg, Martin, et al.
(författare)
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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
- 2016
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Ingår i: Technical Digest - International Electron Devices Meeting, IEDM. - 9781467398930 ; 2016-February
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Konferensbidrag (refereegranskat)abstract
- In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.
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| 5. |
- Berg, Martin, et al.
(författare)
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Single Balanced Down-Conversion Mixer Utilizing Indium Arsenide Nanowire MOSFETs
- 2014
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Ingår i: 26th International Conference on Indium Phosphideand Related Materials (IPRM). - 1092-8669.
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Konferensbidrag (refereegranskat)abstract
- We have fabricated single balanced down-conversion mixer circuits using InAs nanowire MOSFETs as both active and passive devices. This is achieved by a combination of electron beam lithography and UV-lithography with a line width of 12 mu m. The circuits exhibit a low frequency voltage conversion gain of 6 dB, a -3 dB cutoff frequency of 2 GHz and a power consumption of 3.8 mW, while operating at a supply voltage of 1.5 V. The circuits retain circuit functionality even for a supply voltage of 1 V.
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| 6. |
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| 7. |
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| 8. |
- Egard, Mikael, et al.
(författare)
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Vertical InAs nanowire wrap gate transistors with f(t) > 7 GHz and f(max) > 20 GHz.
- 2010
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Ingår i: Nano Letters. - : American Chemical Society (ACS). - 1530-6992 .- 1530-6984. ; 10:3, s. 809-812
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Tidskriftsartikel (refereegranskat)abstract
- In this letter we report on high-frequency measurements on vertically standing III-V nanowire wrap-gate MOSFETs (metal-oxide-semiconductor field-effect transistors). The nanowire transistors are fabricated from InAs nanowires that are epitaxially grown on a semi-insulating InP substrate. All three terminals of the MOSFETs are defined by wrap around contacts. This makes it possible to perform high-frequency measurements on the vertical InAs MOSFETs. We present S-parameter measurements performed on a matrix consisting of 70 InAs nanowire MOSFETs, which have a gate length of about 100 nm. The highest unity current gain cutoff frequency, f(t), extracted from these measurements is 7.4 GHz and the maximum frequency of oscillation, f(max), is higher than 20 GHz. This demonstrates that this is a viable technique for fabricating high-frequency integrated circuits consisting of vertical nanowires.
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| 9. |
- Lind, Erik, et al.
(författare)
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High Frequency Performance of Vertical InAs Nanowire MOSFET
- 2010
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Ingår i: 2010 22Nd International Conference On Indium Phosphide And Related Materials (Iprm). - 1092-8669. - 9781424459193
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Konferensbidrag (refereegranskat)abstract
- We report on RF characterization of vertical, 100-nm-gate length InAs nanowire MOSFETs, utilizing wrap-gate technology and Al2O3 high-kappa gate oxide. The transistors show f(t)=5.6 GHz and f(max)=22 GHz, mainly limited by parasitic capacitances. The RF device performance is described using a hybrid-pi model taking hole generation at the drain into account. Electrostatic modeling of the parasitic capacitances for arrays of vertical nanowires indicates that a strong reduction in extrinsic capacitances can be achieved for devices with a small inter-wire separation.
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| 10. |
- Persson, Karl-Magnus, et al.
(författare)
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1/f-noise in Vertical InAs Nanowire Transistors
- 2013
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Ingår i: 2013 International Conference on Indium Phosphide and Related Materials (IPRM). - 1092-8669. ; , s. 1-2
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Konferensbidrag (refereegranskat)abstract
- The material quality at high-k interfaces are a major concern for FET devices. We study the effect on two types of InAs nanowire (NW) transistors and compare their characteristics. It is found that by introducing an inner layer of Al2O3 at the high-kappa interface, the low frequency noise (LFN) performance regarding gate voltage noise spectral density, S-Vg, is improved by one order of magnitude per unit gate area.
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