| 1. |
- Wang, Deyu, et al.
(author)
-
Memristor-Based In-Circuit Computation for Trace-Based STDP
- 2022
-
In: 2022 Ieee International Conference On Artificial Intelligence Circuits And Systems (Aicas 2022). - : Institute of Electrical and Electronics Engineers (IEEE). ; , s. 1-4
-
Conference paper (peer-reviewed)abstract
- Recently, memristors have been widely used to implement Spiking Neural Networks (SNNs), which is promising in edge computing scenarios. However, most memristor-based SNN implementations adopt simplified spike-timing-dependent plasticity (STDP) for the online learning process. It is challenging for memristor-based implementations to support the trace-based STDP learning rules that have been widely used in neuromorphic applications. This paper proposed a versatile memristor-based architecture to implement the synaptic-level trace-based STDP learning rules. Especially, the similarity between synaptic trace dynamics and the memristor nonlinearity is explored and exploited to emulate the trace variables of trace-based STDP. As two typical trace-based STDP learning rules, the pairwise STDP and the triplet STDP, are simulated on two typical nonlinear bipolar memristor devices. The simulation results show that the behavior of physical memristor devices can be well estimated (below 6% in terms of the relative root-mean-square error), and the memristor-based in-circuit computation for trace-based STDP learning rules can achieve a high correlation coefficient over 98%.
|
|
| 2. |
- Xu, Jiawei, et al.
(author)
-
A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation
- 2021
-
In: 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Conference paper (peer-reviewed)abstract
- This paper proposes a concise window function to build a memristor model, simulating the widely-observed non-linear dopant drift phenomenon of the memristor. Exploiting the non-linearity, the memristor model is applied to the in-situ neuromorphic solution for a cortex-inspired spiking neural network (SNN), spike-based Bayesian Confidence Propagation Neural Network (BCPNN). The improved memristor model utilizing the proposed window function is able to retain the boundary effect and resolve the boundary lock and inflexibility problem, while it is simple in form that can facilitate large-scale neuromorphic model simulation. Compared with the state-of-the-art general memristor model, the proposed memristor model can achieve a 5.8x reduction of simulation time at a competitive fitting level in cortex-comparable large-scale software simulation. The evaluation results show an explicit similarity between the non-linear dopant drift phenomenon of the memristor and the BCPNN learning rule, and the memristor model is able to emulate the key traces of BCPNN with a correlation coefficient over 0.99.
|
|
| 3. |
- Zhang, Wei, et al.
(author)
-
Hierarchical Design of a Low Power Standing Wave Oscillator Based Clock Distribution Network
- 2016
-
In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS). - : IEEE conference proceedings. - 9781509010950
-
Conference paper (peer-reviewed)abstract
- This paper introduces a hierarchical clock interconnection network with two-level bufferless standing wave resonant clock distribution to minimize the clock power consumption in a synchronous system. The first level is a serpentine network which consists of many coupled standing wave oscillators to distribute clock signals in the whole chip area. The second level is a group of fishbone architectures connected to the standing wave oscillators to route clock signals in the local areas. A clock synthesis flow for the fishbone architecture is also introduced to enable design automation. This fishbone architecture is studied through a pipelined floating-point fused multiply-add module under 28nm standard CMOS process. Simulation results show that, this architecture can reduce more than 30% clock power consumption compared with a traditional buffered clock network.
|
|
| 4. |
- Zheng, Lirong, et al.
(author)
-
Future RFID and Wireless Sensors for Ubiquitous Intelligence
- 2008
-
In: 26th Norchip Conference, Norchip. ; , s. 142-149
-
Conference paper (peer-reviewed)abstract
- Next generation RFID towards ubiquitous wireless sensing and identification requires high network throughput along with long operation range and ultra low energy consumption. In this paper, we review future RFID for ubiquitous intelligence and their technology needs from system to device perspectives. As a promising enabling technology, ultra wideband radio (UWB) and its use in various RFID implementations are investigated. A special focus on an UWB/UHF hybrid passive RFID and sensor system with asymmetric wireless links is studied as an example. Unlike conventional RFID systems relying on backscattering and narrowband radio, UWB is introduced as the uplink for tag to reader communication. It enables a high network throughput (2000 tag/sec), high data bandwidth (100MHz pulse rate), under ultra low power and low cost constraint. The hardware implementation in silicon level is also presented. Finally, applications of the system in intelligent warehouse and fresh food tracker are introduced.
|
|
