| 1. |
- Zheng, Lirong, et al.
(författare)
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Photocatalytic activity of ZnO/Sn1-xZnxO2-x nanocatalysts : A synergistic effect of doping and heterojunction
- 2014
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Ingår i: Applied Catalysis B. - : Elsevier BV. - 0926-3373 .- 1873-3883. ; 148, s. 44-50
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Tidskriftsartikel (refereegranskat)abstract
- A novel configuration of porous ZnO/Sn1-xZnxO2-x, heterojunction nanocatalyst with high photocatalytic activity was successfully synthesized through a simple two-step solvothermal method. Porous Sn1-xZnxO2, was synthesized from Zn2+ and Sn4+ precursors with the Zn/Sn ratio of 2:1 in the absence of alkali, and then intermolecular dehydrolysis led to the formation of heterointerface between Sn1-xZnxO2, and ZnO. The results show that Zn2+ doping exhibits a significant influence on particle size of SnO2 leading to much higher specific surface area and larger band gap, which is in favor of the photocatalytic activity of SnO2 under UV light irradiation. In addition, the formation of ZnO/Sn1-xZnxO2 heterostructure improves the separation of photogenerated electron hole pairs due to the potential difference between Sn1-xZnxO2, and ZnO, which also benefits to photocatalysis. By taking account of them together, these results provide further insight into the synergistic effects of metal ion doping and semiconductor/semiconductor heterostructure on the activity of photocatalysts in environmental remediation applications. (C) 2013 Elsevier B.V. All rights reserved.
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| 2. |
- Ling, Li, et al.
(författare)
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Precisely Controlled Hydration Water for Performance Improvement of Organic-Inorganic Perovskite Solar Cells
- 2016
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Ingår i: Advanced Functional Materials. - : Wiley-VCH Verlagsgesellschaft. - 1616-301X .- 1616-3028. ; 26:28, s. 5028-5034
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Tidskriftsartikel (refereegranskat)abstract
- Recently, intensive studies on the role of water molecule in the formation of organic-inorganic perovskite film have been reported. However, not only the contradictive phenomena but also the complex processing technique has hindered the widespread use of water molecule in perovskite preparation. Here the hydration water is introduced into the precursors instead of water. By precisely controlling the content of hydration water, a smoother and more uniform perovskite film is obtained through a simple one-step spin coating method. The improvement of perovskite film quality leads to highly efficient planar perovskite solar cells. Summing up the device studies and the investigation of morphology, crystallization, and optical properties, the impact of water molecule in the formation of perovskite crystal and consequences of device performance is understood. Due to its universal adaptability and simplified process, precise control of hydration water is therefore of great utility to high quality perovskite films fabrication and large-scale production of this upcoming photovoltaic technology.
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| 3. |
- Pang, Zhibo, et al.
(författare)
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A Pervasive and Preventive Healthcare Solution for Medication Noncompliance and Daily Monitoring
- 2009
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Ingår i: 2009 2ND INTERNATIONAL SYMPOSIUM ON APPLIED SCIENCES IN BIOMEDICAL AND COMMUNICATION TECHNOLOGIES (ISABEL 2009). - NEW YORK : IEEE. - 9781424446407 ; , s. 315-320
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Konferensbidrag (refereegranskat)abstract
- Pervasive healthcare solution for medication noncompliance problem would help to save $177 billion annually in the United States. And the rapidly increasing demanding of daily monitoring with onsite diagnosis and prognosis is driving homecare solutions to integrate more and more sensing and data processing capacities. So a powerful system is needed not only to address the medication noncompliance but also to be used as a Pervasive Healthcare Station in home. In this paper, a pervasive and preventive healthcare solution for medication noncompliance and daily monitoring is proposed using an intelligent package sealed by Controlled Delamination Material (CDM) and controlled by Radio Frequency Identification (RFID). Onsite diagnosis and prognosis capacities for kinds of health parameters are supported due to scalable and intensive computing capacitance of the 2D-Mesh-NoC based multi-core architecture. Additionally, friendly human-machine interface is emphasized to make it usable for the elderly, disabled and patients due to enhanced multimedia performance. Experimental results of an implemented prototype confirmed the necessity of the multi-core architecture and approved the feasibility of the proposed intelligent package.
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| 4. |
- Rong, Liang, et al.
(författare)
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RF Transmitter Architecture Investigation for Power Efficient Mobile WiMAX Applications
- 2008
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Ingår i: 2008 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS. - NEW YORK : IEEE. - 9781424425419 ; , s. 114-117
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Konferensbidrag (refereegranskat)abstract
- Wireless broadband digital communication systems with high spectral efficiency suffer from severe power efficiency problem. Peak-to-Average Power Ratio is reported up to 12dB for WiMAX 802.16e systems implementing OFDM IFFT-1024 and 64-QAM modulation. In this work, outphasing (LILAC) and polar transmitter architectures are investigated and compared with direct conversion (DC) architecture. Complete system solution targeting 23dBm output power is evaluated. System level simulation result shows that, with linear power combiner, LILAC consumes more power than DC if non-clipping modulation scheme used. And polar system has stringent 3 degree phase matching and 0.5dB gain matching requirements to meet EVM and spectrum mask specifications.
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| 5. |
- You, Yintao, et al.
(författare)
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An organic multilevel non-volatile memory device based on multiple independent switching modes
- 2014
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Ingår i: Organic electronics. - : Elsevier BV. - 1566-1199 .- 1878-5530. ; 15:9, s. 1983-1989
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Tidskriftsartikel (refereegranskat)abstract
- The demand for higher data density memory structures is greater today than ever before. Multilevel resistive organic memory devices (OMD) provide an ideal solution, in being easily fabricated, cost-effective and at the same time promising high storage capacity. However, conventional methods for multilevel OMDs impose demanding requirements on material properties and attain only limited performance. We hereby provide an alternative design concept that combines multiple switching modes in one device to realize multilevel function. The device possesses a simple structure by using a ferroelectric phase-separated blend as the active layer. Two switching modes, the ferroelectric switching and the metallic filament switching, are realized simultaneously in this device, and enable a ternary storage function. The cross-section scanning electron microscope (SEM) images provide a strong evidence of the formation and annihilation of the metallic filament.
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| 6. |
- Huan, Yuxiang, et al.
(författare)
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A 61 μa/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things
- 2016
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Ingår i: International System on Chip Conference. - : IEEE Computer Society. - 9781467390941 ; , s. 235-239
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Konferensbidrag (refereegranskat)abstract
- This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.
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| 7. |
- Huang, Boming, et al.
(författare)
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Automated trading systems statistical and machine learning methods and hardware implementation : a survey
- 2019
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Ingår i: Enterprise Information Systems. - : Taylor & Francis. - 1751-7575 .- 1751-7583. ; 13:1, s. 132-144
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Tidskriftsartikel (refereegranskat)abstract
- Automated trading, which is also known as algorithmic trading, is a method of using a predesigned computer program to submit a large number of trading orders to an exchange. It is substantially a real-time decision-making system which is under the scope of Enterprise Information System (EIS). With the rapid development of telecommunication and computer technology, the mechanisms underlying automated trading systems have become increasingly diversified. Considerable effort has been exerted by both academia and trading firms towards mining potential factors that may generate significantly higher profits. In this paper, we review studies on trading systems built using various methods and empirically evaluate the methods by grouping them into three types: technical analyses, textual analyses and high-frequency trading. Then, we evaluate the advantages and disadvantages of each method and assess their future prospects.
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| 8. |
- Huang, Boming, et al.
(författare)
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IECA : An In-Execution Configuration CNN Accelerator With 30.55 GOPS/mm(2) Area Efficiency
- 2021
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Ingår i: IEEE Transactions on Circuits and Systems Part 1. - : Institute of Electrical and Electronics Engineers (IEEE). - 1549-8328 .- 1558-0806. ; 68:11, s. 4672-4685
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Tidskriftsartikel (refereegranskat)abstract
- It remains challenging for a Convolutional Neural Network (CNN) accelerator to maintain high hardware utilization and low processing latency with restricted on-chip memory. This paper presents an In-Execution Configuration Accelerator (IECA) that realizes an efficient control scheme, exploring architectural data reuse, unified in-execution controlling, and pipelined latency hiding to minimize configuration overhead out of the computation scope. The proposed IECA achieves row-wise convolution with tiny distributed buffers and reduces the size of total on-chip memory by removing 40% of redundant memory storage with shared delay chains. By exploiting a reconfigurable Sequence Mapping Table (SMT) and Finite State Machine (FSM) control, the chip realizes cycle-accurate Processing Element (PE) control, automatic loop tiling and latency hiding without extra time slots for pre-configuration. Evaluated on AlexNet and VGG-16, the IECA retains over 97.3% PE utilization and over 95.6% memory access time hiding on average. The chip is designed and fabricated in a UMC 55-nm process running at a frequency of 250 MHz and achieves an area efficiency of 30.55 GOPS/mm(2) and 0.244 GOPS/KGE (kilo-gate-equivalent), which makes an over 2.0x and 2.1x improvement, respectively, compared with that of previous related works. Implementation of the IEC control scheme uses only a 0.55% area of the 2.75 mm(2) core.
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| 9. |
- Liu, Lizheng, et al.
(författare)
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A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
- 2018
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Ingår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems. - : Institute of Electrical and Electronics Engineers (IEEE). - 1063-8210 .- 1557-9999. ; 26:10, s. 2143-2154
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Tidskriftsartikel (refereegranskat)abstract
- The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.
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| 10. |
- Liu, Lizheng, et al.
(författare)
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An Autonomous Error-Tolerant Architecture Featuring Self-reparation for Convolutional Neural Networks
- 2020
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Ingår i: Proceeding of the IEEE Vehicular Technology Conference. - : Institute of Electrical and Electronics Engineers (IEEE).
-
Konferensbidrag (refereegranskat)abstract
- Convolutional neural networks are widely used in artificial intelligence and Internet of Things area. As the scale of convolutional neural network expands, more and more processing units are provided for it. The systems are easy prone to error, and any computing problems in any layer of the network will lead to wrong output results. Traditional multimode redundancy methods make the systems more complex, and increase power consumption. This paper proposes an autonomous error-tolerant architecture for convolutional neural networks. Taking the LeNet-5 as an example, the network layers of CNN are mapped on the AET architecture, an error-tolerant synapse is designed to discover the errors, an active evolution scheme is designed to handle unrecoverable errors and implement network reconfiguration. This design is implemented on FPGA, and the experimental results show that this architecture can realize effective error tolerance for convolutional neural network and has fast error recovery ability under the premise of ensuring the same recognition accuracy.
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