| 1. |
- Amin, Yasar
(author)
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Printable Green RFID Antennas for Embedded Sensors
- 2013
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Doctoral thesis (other academic/artistic)abstract
- In the recent years, radio-frequency identification (RFID) technology has been widely integrated into modern society applications, ranging from barcode successor to retail supply chain, remote monitoring, detection and healthcare, for instance. In general, an RFID tag or transponder is composed of an antenna and an application-specific integrated circuit chip. In a passive UHF RFID system (which is the focus of presented research), the communication between the transponder tag and the reader is established by modulating the radar cross section (RCS) of the transponder tag. The need for flexible RFID tags has recently been increased enormously; particularly the RFID tags for the UHF band ensure the widest use but in the meantime face considerable challenges of cost, reliability and environmental friendliness.The multidimensional focus of the aforementioned research encompasses the production of low-cost and reliable RFID tags. The state-of-the-art fabrication methods and materials for proposed antennas are evaluated in order to surmount the hurdles for realization of flexible green electronics. Moreover, this work addresses the new rising issues interrelated to the field of economic and eco-friendly tags comprising of paper substrate. Paper substrates offer numerous advantages for manufacturing RFID tags, not only is paper extensively available, and inexpensive; it is lightweight, recyclable and can be rolled or folded into 3D configurations.The most important aspect of an RFID system's performance is the reading range. In this research several pivotal challenges for item-level tagging, are resolved by evolving novel structures of progressive meander line, quadrate bowtie and rounded corner bowtie antennas in order to maximize the reading distance with a prior selected microchip under the various constraints (such as limited antenna size, specific antenna impedance, radiation pattern requirements). This approach is rigorously evolved for the realization of innovative RFID tag antenna which has incorporated humidity sensor functionality along with calibration mechanism due to distinctiveness of its structural behavior which will be an optimal choice for future ubiquitous wireless sensor network (WSN) modules.The RFID market has grown in a two-dimensional trend, one side constitutes standalone RFID systems. On the other side, more ultramodern approach is paving its way, in which RFID needs to be integrated with broad operational array of distinct applications for performing different functions including sensors, navigation, broadcasting, and personal communication, to mention a few. Using different antennas to include all communication bands is a straightforward approach, but at the same time, it leads to increase cost, weight, more surface area for installation, and above all electromagnetic compatibility issues. The indicated predicament is solved by realization of proposed single wideband planar spirals and sinuous antennas which covers several bands from 0.8-3.0GHz. These antennas exhibit exceptional performance throughout the operational range of significance, thus paving the way for developing eco-friendly multi-module RF industrial solutions.
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| 2. |
- Shen, Jue
(author)
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Interactive RFID for Industrial and Healthcare Applications
- 2015
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Doctoral thesis (other academic/artistic)abstract
- This thesis introduces the circuit and system design of interactive Radio-Frequency Identification (RFID) for Internet of Things (IoT) applications. IoT has the vision of connectivity for anything, at anytime and anywhere. One of the most important characteristics of IoT is the automatic and massive interaction of real physical world (things and human) with the virtual Internet world.RFID tags integrated with sensors have been considered as one suitable technology for realizing the interaction. However, while it is important to have RFID tags with sensors as the input interaction, it is also important to have RFID tags with displays as the output interaction.Display interfaces vary based on the information and application scenarios. On one side, remote and centralized display interface is more suitable for scenarios such as monitoring and localization. On the other side, tag level display interface is more suitable for scenarios such as object identification and online to offline propagation.For tag level display, though a substantial number of researches have focused on introducing sensing functionalities to low power Ultra-High Frequency (UHF) RFID tags, few works address UHF RFID tags with display interfaces. Power consumption and integration with display of rigid substrate are two main challenges.With the recent emerging of Electronic Paper Display (EPD) technologies, it becomes possible to overcome the two challenges. EPD resembles ordinary ink on paper by characteristics of substrate flexibility, pattern printability and material bi-stability. Average power consumption of display is significantly reduced due to bi-stability, the ability to hold color for certain periods without power supplies. Among different EPD types, Electrochromic (EC) display shows advantage of low driving voltage compatible to chip supply voltage.Therefore this thesis designs a low power UHF RFID tag integrated in 180 nm CMOS process with inkjet-printed EC polyimide display. For applications where refresh rate is ultra-low (such as electronic label in retailing and warehouse), the wireless display tag is passive and supplied by the energy harvested from UHF RF wave. For applications where refresh rate is not ultra-low (such as object identification label in mass customized manufacturing), the wireless display tag is semi-passive and supplied by soft battery. It works at low average power consumption and with out-of-battery alert.For remote and centralized display, the limitations of uplink (from tags to reader) capacity and massive-tag information feedback in IoT scenarios is the main challenge. Compared to conventional UHF RFID backscattering whose data rate is limited within hundreds of kb/s, Ultra-wideband (UWB) transmission have been verified with the performance of Mb/s data rate with several tens of pJ/pulse energy consumption.Therefore, a circuit prototype of UHF/UWB RFID tag replacing UHF backscattering with UWB transmitter is implemented. It also consists of Analog-to-Digital Converter (ADC) and Electrocardiogram (ECG) electrodes for healthcare applications of real-time remote monitoring of multiple patients ECG signals. The ECG electrodes are fabricated on paper substrate by inkjet printing to improve patient comfort.Key contribution of the thesis includes: 1) the power management scheme and circuit design of passive UHF/UWB RFID display tag. The tag sensitivity (the input RF power) is -10.5 dBm for EC display driving, comparable to the performance of conventional passive UHF RFID tags without display functions, and -18.5 dBm for UWB transmission, comparable to the state-of-the-art performance of passive UHF RFID tag. 2) communication flow and circuit design of UHF/UWB RFID tag with ECG sensing. The optimum system throughout is 400 tags/second with 1.5 KHz ECG sampling rate and 10 Mb/s UWB pulse rate.
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| 3. |
- Weldezion, Awet Yemane
(author)
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Exploring the Scalability and Performance of Networks-on-Chip with Deflection Routing in 3D Many-core Architecture
- 2016
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Doctoral thesis (other academic/artistic)abstract
- Three-Dimensional (3D) integration of circuits based on die and wafer stacking using through-silicon-via is a critical technology in enabling "more-than-Moore", i.e. functional integration of devices beyond pure scaling ("more Moore"). In particular, the scaling from multi-core to many-core architecture is an excellent candidate for such integration. 3D systems design follows is a challenging and a complex design process involving integration of heterogeneous technologies. It is also expensive to prototype because the 3D industrial ecosystem is not yet complete and ready for low-cost mass production. Networks-on-Chip (NoCs) efficiently facilitates the communication of massively integrated cores on 3D many-core architecture. In this thesis scalability and performance issues of NoCs are explored in terms of architecture, organization and functionality of many-core systems.First, we evaluate on-chip network performance in massively integrated many-core architecture when network size grows. We propose link and channel models to analyze the network traffic and hence the performance. We develop a NoC simulation framework to evaluate the performance of a deflection routing network as the architecture scales up to 1000 cores. We propose and perform comparative analysis of 3D processor-memory model configurations in scalable many-core architectures.Second, we investigate how the deflection routing NoCs can be designed to maximize the benefit of the fast TSVs through clock pumping techniques. We propose multi-rate models for inter-layer communication. We quantify the performance benefit through cycle-accurate simulations for various configurations of 3D architectures.Finally, the complexity of massively integrated many-core architecture by itself brings a multitude of design challenges such as high-cost of prototyping, increasing complexity of the technology, irregularity of the communication network, and lack of reliable simulation models. We formulate a zero-load average distance model that accurately predicts the performance of deflection routing networks in the absence of data flow by capturing the average distance of a packet with spatial and temporal probability distributions of traffic.The thesis research goals are to explore the design space of vertical integration for many-core applications, and to provide solutions to 3D technology challenges through architectural innovations. We believe the research findings presented in the thesis work contribute in addressing few of the many challenges to the field of combined research in many-core architectural design and 3D integration technology.
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| 4. |
- Ma, Ning
(author)
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Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing
- 2015
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Doctoral thesis (other academic/artistic)abstract
- The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency.To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs.Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW.When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes.In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.
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| 5. |
- Mao, Jia
(author)
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Radio and Sensor Interfaces for Energy-autonomous Wireless Sensing
- 2016
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Doctoral thesis (other academic/artistic)abstract
- Along with rapid development of sensing and communication technology, Internet of Things (IoTs) has enabled a tremendous number of applications in health care, agriculture, and industry. As the fundamental element, the wireless sensing node, such as radio tags need to be operating under micro power level for energy autonomy. The evolution of electronics towards highly energy-efficient systems requires joint efforts in developing innovative architectures and circuit techniques. In this dissertation, we explore ultra-low power circuits and systems for micropower wireless sensing in the context of IoTs, with a special focus on radio interfaces and sensor interfaces. The system architecture of UHF/UWB asymmetric radio is introduced firstly. The active UWB radio is employed for the tag-to-reader communication while the conventional UHF radio is used to power up and inventory the tag. On the tag side, an ultra-low power, high pulse swing, and power scalable UWB transmitter is studied. On the reader side, an asymmetric UHF/UWB reader is designed. Secondly, to eliminate power-hungry frequency synthesis circuitry, an energy-efficient UWB transmitter with wireless clock harvesting is presented. The transmitter is powered by an UHF signal wirelessly and respond UWB pulses by locking-gating-amplifying the sub-harmonic of the UHF signal. 21% locking range can be achieved to prevent PVT variations with -15 dBm injected power. Finally, radio-sensing interface co-design is explored. Taking the advantage of RC readout circuit and UWB pulse generator, the sensing information is directly extracted and transmitted in the time domain, exploiting high time-domain resolution UWB pulses. It eliminates the need of ADC of the sensor interface, meanwhile, reduces the number of bits to be transmitted for energy saving. The measurement results show that the proposed system exhibits 7.7 bits ENOB with an average relative error of 0.42%.
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| 6. |
- Qin, Yajie, 1979-
(author)
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Low Power Analog Interface Circuits toward Software Defined Sensors
- 2016
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Doctoral thesis (other academic/artistic)abstract
- Internet of Things is expanding to the areas such as healthcare, home management, industrial, agriculture, and becoming pervasive in our life, resulting in improved efficiency, accuracy and economic benefits. Smart sensors with embedded interfacing integrated circuits (ICs) are important enablers, hence, variety of smart sensors are required. However, each type of sensor requires specific interfacing chips, which divides the huge market of sensors’ interface chips into lots of niche markets, resulting in high develop cost and long time-to-market period for each type. Software defined sensor is regarded as a promising solution, which is expected to use a flexible interface platform to cover different sensors, deliver specificity through software programming, and integrate easily into the Internet of Things. In this work, research is carried out on the design and implementations of ultra low power analog interface circuits toward software defined sensors for healthcare services based on Internet of Things. This thesis first explores architectures and circuit techniques for energy-efficient and flexible analog to digital conversion. A time-spreading digital calibration, to calibrate the errors due to finite gain and capacitor mismatch in multi-bit/stage pipelined converters, is developed with short convergence time. The effectiveness of the proposed technique is demonstrated with intensive simulations. Two novel circuit level techniques, which can be combined with digital calibration techniques to further improve the energy efficiency of the converters, are also presented. One is the Common-Mode-Sensing-and-Input-Interchanging (CSII) operational-transconductance-amplifier (OTA) sharing technique to enable eliminating potential memory effects. The other is a workload-balanced multiplying digital-to-analog converter (MDAC) architecture to improve the settling efficiency of a high linear multi-bit stage. Two prototype converters have been designed and fabricated in 0.13 μm CMOS technology. The first one is a 14 bit 50 MS/s digital calibrated pipelined analog to digital converter that employs the workload-balanced MDAC architecture and time-spreading digital calibration technique to achieve improved power-linearity tradeoff. The second one is a 1.2 V 12 bit 5~45 MS/s speed and power-scalable ADC incorporating the CSII OTA-sharing technique, sample-and-hold-amplifier-free topology and adjustable current bias of the building blocks to minimize the power consumption. The detailed measurement results of both converters are reported and deliver the experimental verification of the proposed techniques. Secondly, this research investigates ultra-low-power analog front-end circuits providing programmability and being suitable for different types of sensors. A pulse-width- -modulation-based architecture with a folded reference is proposed and proven in a 0.18 μm technology to achieve high sensitivity and enlarged dynamic range when sensing the weak current signals. A 8-channel bio-electric sensing front-end, fabricated in a 0.35 μm CMOS technology is also presented that achieves an input impedance of 1 GΩ, input referred noise of 0.97 Vrms and common mode rejection ratio of 114 dB. With the programmable gain and cut-off frequency, the front-end can be configured to monitor for long-term a variety of bio-electric signals, such as electrooculogram (EOG), electromyogram (EMG), electroencephalogram (EEG) and electrocardiogram (ECG) signals. The proposed front-end is integrated with dry electrodes, a microprocessor and wireless link to build a battery powered E-patch for long-term and continuous monitoring. In-vivo test results with dry electrodes in the field trials of sitting, standing, walking and running slowly, show that the quality of ECG signal sensed by the E-patch satisfies the requirements for preventive cardiac care. Finally, a wireless multimodal bio-electric sensor system is presented. Enabled by a customized flexible mixed-signal system on chip (SoC), this bio-electric sensor system is able to be configured for ECG/EMG/EEG recording, bio-impedance sensing, weak current stimulation, and other promising functions with biofeedback. The customized SoC, fabricated in a 0.18 μm CMOS technology, integrates a tunable analog front-end, a 10 bit ADC, a 14 bit sigma-delta digital to current converter, a 12 bit digital to voltage converter, a digital accelerator for wavelet transformation and data compression, and a serial communication protocol. Measurement results indicate that the SoC could support the versatile bio-electric sensor to operate in various applications according to specific requirements.
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| 7. |
- Shao, Botao, 1981-
(author)
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Fully Printed Chipless RFID Tags towards Item-Level Tracking Applications
- 2014
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Doctoral thesis (other academic/artistic)abstract
- An ID generating circuit is unquestionably the core of a chipless RFID tag. For convenience of printing process and cost consideration, the circuit should be kept as simple as possible. Based on the cognition, an 8-bit time-domain based ID generating circuit that merely consists of a ML and eight capacitors was offered, and implemented on photo-paper substrates via inkjet printing process. In addition to the experimental measurements, the circuit was also input into circuit simulators for cross-validation. The good agreement between simulations and measurements is observed, exhibiting the tag technical feasibility. Besides of low cost, the tag has wide compatibility with current licensed RFID spectrum, which will facilitate the future deployment in real applications.Compared to time-domain based chipless tags, frequency signatures based chipless RFID tags are expected to offer a larger coding capacity. As a response, we presented a 10-bit frequency-domain based chipless RFID tag. The tag composed of ten configurable LC resonators was implemented on flexible polyimide substrate by using fast toner-transferring process. Field measurements revealed not only the practicability of the tag, but also the high signal to noise ratio (SNR). Another frequency domain tag consists of a configurable coplanar LC resonator. With the use of all printing process, the tag was for the first time realized on common packaging papers. The tag feasibility was confirmed by subsequent measurements. Owing to the ultra-low cost potential and large SNR, The tag may find wide applications in typical RFID solutions such as management of paper tickets for social events and governing of smart documents.Ultra wide band (UWB) technology possesses a number of inherent merits such as high speed communication and large capacity, multi-path immunity, accurate ranging and positioning, penetration through obstacles, as well as extremely low-cost and low- power transmitters. Thus, passive UWB RFIDs are expected to play an important pole in the future identification applications for IoT. We explained the feature difference between UWB chipless tags and chip based tags, and forecasted the applications respectively based on the comparison between the two technologies. It is expected that the two technologies will coexist and compensate each other in the applications of IoT.Lastly, the thesis ends up with brief summary of the author’s contributions, and technical prospect for the future development of printable chipless RFID tags.
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