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| 2. |
- Fröberg, Linus, et al.
(författare)
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Vertical InAs nanowire wrap-gate FETs
- 2006
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Ingår i: Book of abstracts: Semicond Nanowires Symp, Eindhoven, The Netherlands (2006).
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Konferensbidrag (refereegranskat)
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| 3. |
- Lind, Erik, et al.
(författare)
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Improved subthreshold slope in an InAs nanowire heterostructure field-effect transistor
- 2006
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Ingår i: Nano Letters. - : American Chemical Society (ACS). - 1530-6992 .- 1530-6984. ; 6:9, s. 1842-1846
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Tidskriftsartikel (refereegranskat)abstract
- An n-type InAs/InAsP heterostructure nanowire field-effect transistor has been fabricated and compared with a homogeneous InAs field-effect transistor. For the same device geometry, by introduction of the heterostructure, the threshold voltage is shifted 4 V, the maximum current on-off ratio is enhanced by a factor of 10 000, and the subthreshold swing is lowered by a factor 4 compared to the homogeneous transistor. At the same time, the drive current remains constant for a fixed gate overdrive. A single nanowire heterostructure transistor has a transconductance of 5 mu A/V at a low source-drain voltage of 0.3 V. For the homogeneous InAs transistor, we deduced a high electron mobility of 1500 cm(2)/Vs.
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| 4. |
- Thelander, Claes, et al.
(författare)
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Development of a Vertical Wrap-Gated InAs FET
- 2008
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Ingår i: IEEE Transactions on Electron Devices. - 0018-9383. ; 55:11, s. 3030-3036
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Tidskriftsartikel (refereegranskat)abstract
- In this paper, we report on the development of a vertical wrap-gated field-effect transistor based on epitaxially grown InAs nanowires. We discuss some of the important steps involved in the growth and processing, such as nanowire position control in situ doping, high-kappa dielectric deposition, spacer layer formation: and metal wrap-gate fabrication. In particular, we compare a few alternative methods for deposition of materials onto vertical structures and discuss their potential advantages and limitations. Finally, we also present a comparison of transistor performance for nanowires grown using two different epitaxial techniques.
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| 5. |
- Wernersson, Lars-Erik, et al.
(författare)
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Nanowire field-effect transistor
- 2007
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Ingår i: Japanese Journal of Applied Physics. - 0021-4922. ; 46:4B, s. 2629-2631
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Tidskriftsartikel (refereegranskat)abstract
- A new processing scheme for the fabrication of sub-100-nm-gate-length vertical nanowire transistors has been developed. InAs transistors with an 11 x 11 nanowire matrix and 80 nm gate length have been realized by this process. The gate length is directly controlled via the thickness of the evaporated gate metal and is thus easily scalable. The demonstrated devices operate in depletion mode, and they show a maximum drive current of about 1 mA and a maximum transconductance of 0.52 mS at V-g = -0.5 V and V-d = 1 V.
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| 6. |
- Wernersson, Lars-Erik, et al.
(författare)
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Wrap-gated InAs nanowire field-effect transistor
- 2005
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Ingår i: International Electron Devices Meeting 2005. - 078039268X ; , s. 273-276
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Konferensbidrag (refereegranskat)abstract
- Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at Vds ≡ 0.15 V (for Vg ≡ 0 V) and low voltage operation Vth ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design
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| 7. |
- Borg, Mattias, et al.
(författare)
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GaAs/GaSb nanowire heterostructures grown by MOVPE
- 2008
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Ingår i: Journal of Crystal Growth. - : Elsevier BV. - 0022-0248. ; 310:18, s. 4115-4121
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Tidskriftsartikel (refereegranskat)abstract
- We report Au-assisted growth of GaAs/GaSb nanowire heterostructures on GaAs(1 1 1)B-substrates by metal-organic vapor phase epitaxy. The growth is studied at various precursor molar fractions and temperatures, in order to optimize the growth conditions for the GaSb nanowire segment. In contrast to most other III-V nanowire systems, the GaSb nanowire growth is Group V-limited under most conditions. We found that depending on the TMSb molar fraction, the seed particle is either supersaturated AuGa or AuGa2 during GaSb growth. The high Ga content in the particle gives a characteristic diameter increase between the GaAs and GaSb segment. From TEM and XEDS measurements we conclude that the GaSb nanowire growth occurs along either the AuGa-GaSb or AuGa2-GaSb pseudo-binaries of the Au-Ga-Sb ternary phase diagram. Finally, the GaSb nanowires exhibit untapered radial growth on the {1 (1) over bar 0} side facets. (C) 2008 Elsevier B.V. All rights reserved.
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| 8. |
- Bryllert, Tomas, et al.
(författare)
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Vertical high-mobility wrap-gated InAs nanowire transistor
- 2006
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Ingår i: IEEE Electron Device Letters. - 0741-3106 .- 1558-0563. ; 27:5, s. 323-325
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Tidskriftsartikel (refereegranskat)abstract
- In this letter, the authors demonstrate a vertical wrap-gated field-effect transistor based on InAs nanowires [Proc. DRC, 2005, p. 157]. The nanowires have a diameter of 80 nm and are grown using selective epitaxy; a matrix of typically 10 x 10 vertically standing wires is used as channel in the transistor. The authors measure current saturation at V-ds = 0.15 V (V-g = 0 V), and a high mobility, compared to the previous nanowire transistors, is deduced.
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| 9. |
- Bryllert, Tomas, et al.
(författare)
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Vertical high mobility wrap-gated InAs nanowire transistor
- 2005
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Ingår i: 63rd Device Research Conference Digest, 2005. DRC '05. - 0780390407 ; 1
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Konferensbidrag (refereegranskat)abstract
- We demonstrate a wrap-gated field effect transistor based on a matrix of vertically standing InAs nanowires (Jensen, et. al., 2004). A lower limit of the mobility, derived from the transconductance, is on the order of 3000 cm2/Vs. The narrow ~100 nm channels show excellent current saturation and a threshold of Vg = -0.15 V. The sub-threshold characteristics show a close to ideal slope of 62mV/decade over two orders of magnitude
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| 10. |
- Bryllert, Tomas, et al.
(författare)
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Vertical wrap-gated nanowire transistors
- 2006
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Ingår i: Nanotechnology. - 0957-4484. ; 17:11, s. 227-230
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Tidskriftsartikel (refereegranskat)abstract
- We present a process for fabricating a field-effect transistor based on vertically standing InAs nanowires and demonstrate initial device characteristics. The wires are grown by chemical beam epitaxy at lithographically defined locations. Wrap gates are formed around the base of the wires through a number of deposition and etch steps. The fabrication is based on standard III - V processing and includes no random elements or single nanowire manipulation.
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